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Searched refs:GENMO_WT__VGA_HSYNC_POL_MASK (Results 1 – 7 of 7) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/dce/
HDdce_6_0_sh_mask.h7167 #define GENMO_WT__VGA_HSYNC_POL_MASK 0x00000040L macro
HDdce_8_0_sh_mask.h10613 #define GENMO_WT__VGA_HSYNC_POL_MASK 0x40 macro
HDdce_10_0_sh_mask.h10997 #define GENMO_WT__VGA_HSYNC_POL_MASK 0x40 macro
HDdce_11_0_sh_mask.h10809 #define GENMO_WT__VGA_HSYNC_POL_MASK 0x40 macro
HDdce_11_2_sh_mask.h12063 #define GENMO_WT__VGA_HSYNC_POL_MASK 0x40 macro
HDdce_12_0_sh_mask.h2213 #define GENMO_WT__VGA_HSYNC_POL_MASK … macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/dcn/
HDdcn_1_0_sh_mask.h852 #define GENMO_WT__VGA_HSYNC_POL_MASK … macro