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Searched refs:EVERGREEN_CRTC1_REGISTER_OFFSET (Results 1 – 9 of 9) sorted by relevance

/dragonfly/sys/dev/drm/radeon/
HDevergreen_reg.h225 #define EVERGREEN_CRTC1_REGISTER_OFFSET (0x79f0 - 0x6df0) macro
HDradeon_display.c1523 EVERGREEN_CRTC1_REGISTER_OFFSET, in radeon_afmt_init()
1857 EVERGREEN_CRTC1_REGISTER_OFFSET); in radeon_get_crtc_scanoutpos()
1859 EVERGREEN_CRTC1_REGISTER_OFFSET); in radeon_get_crtc_scanoutpos()
HDcik.c6930 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
6942 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
7213 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2); in cik_irq_set()
7226 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, in cik_irq_set()
7279 EVERGREEN_CRTC1_REGISTER_OFFSET); in cik_irq_ack()
7297 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, in cik_irq_ack()
7304 WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK); in cik_irq_ack()
7306 WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK); in cik_irq_ack()
HDradeon_dp_mst.c15 EVERGREEN_CRTC1_REGISTER_OFFSET, in radeon_atom_set_enc_offset()
HDradeon_device.c700 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET); in radeon_card_posted()
HDevergreen_cs.c1028 EVERGREEN_VLINE_START_END + EVERGREEN_CRTC1_REGISTER_OFFSET, in evergreen_cs_packet_parse_vline()
1036 EVERGREEN_VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, in evergreen_cs_packet_parse_vline()
HDatombios_crtc.c2235 radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET; in radeon_atombios_init_crtc()
HDevergreen.c114 EVERGREEN_CRTC1_REGISTER_OFFSET,
HDsi.c135 EVERGREEN_CRTC1_REGISTER_OFFSET,