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Searched refs:DPLL_VGA_MODE_DIS (Results 1 – 3 of 3) sorted by relevance

/dragonfly/sys/dev/drm/i915/
HDintel_display.c1501 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0); in chv_enable_pll()
1603 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS); in i9xx_disable_pll()
1615 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; in vlv_disable_pll()
1632 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; in chv_disable_pll()
6540 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; in vlv_compute_dpll()
6557 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; in chv_compute_dpll()
6838 dpll = DPLL_VGA_MODE_DIS; in i9xx_compute_dpll()
6912 dpll = DPLL_VGA_MODE_DIS; in i8xx_compute_dpll()
14635 DPLL_VGA_MODE_DIS | in i830_enable_pipe()
14657 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS); in i830_enable_pipe()
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HDintel_runtime_pm.c913 val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; in vlv_display_power_well_init()
HDi915_reg.h3085 #define DPLL_VGA_MODE_DIS (1 << 28) macro