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Searched refs:DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK (Results 1 – 2 of 2) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/dcn/
HDdcn_1_0_sh_mask.h35331 #define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK … macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/dce/
HDdce_12_0_sh_mask.h41557 #define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK … macro