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Searched refs:DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR__SHIFT (Results 1 – 7 of 7) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/dce/
HDdce_6_0_sh_mask.h5802 #define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR__SHIFT 0x0000001b macro
HDdce_8_0_sh_mask.h7964 #define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR__SHIFT 0x1b macro
HDdce_10_0_sh_mask.h6992 #define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR__SHIFT 0x1b macro
HDdce_11_0_sh_mask.h6894 #define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR__SHIFT 0x1b macro
HDdce_11_2_sh_mask.h7966 #define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR__SHIFT 0x1b macro
HDdce_12_0_sh_mask.h4862 #define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR__SHIFT … macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/dcn/
HDdcn_1_0_sh_mask.h3828 #define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR__SHIFT … macro