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Searched refs:DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED_MASK (Results 1 – 7 of 7) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/dce/
HDdce_6_0_sh_mask.h5791 #define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED_MASK 0x01000000L macro
HDdce_8_0_sh_mask.h7949 #define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED_MASK 0x1000000 macro
HDdce_10_0_sh_mask.h6977 #define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED_MASK 0x1000000 macro
HDdce_11_0_sh_mask.h6879 #define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED_MASK 0x1000000 macro
HDdce_11_2_sh_mask.h7951 #define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED_MASK 0x1000000 macro
HDdce_12_0_sh_mask.h4909 #define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED_MASK … macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/dcn/
HDdcn_1_0_sh_mask.h3871 #define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED_MASK … macro