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Searched refs:DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED_MASK (Results 1 – 7 of 7) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/dce/
HDdce_6_0_sh_mask.h5777 #define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED_MASK 0x00000008L macro
HDdce_8_0_sh_mask.h7885 #define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED_MASK 0x8 macro
HDdce_10_0_sh_mask.h6905 #define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED_MASK 0x8 macro
HDdce_11_0_sh_mask.h6799 #define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED_MASK 0x8 macro
HDdce_11_2_sh_mask.h7879 #define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED_MASK 0x8 macro
HDdce_12_0_sh_mask.h4873 #define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED_MASK … macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/dcn/
HDdcn_1_0_sh_mask.h3839 #define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED_MASK … macro