Searched refs:DMA1_REGISTER_OFFSET (Results 1 – 5 of 5) sorted by relevance
62 reg = DMA_RB_RPTR + DMA1_REGISTER_OFFSET; in cayman_dma_get_rptr()86 reg = DMA_RB_WPTR + DMA1_REGISTER_OFFSET; in cayman_dma_get_wptr()107 reg = DMA_RB_WPTR + DMA1_REGISTER_OFFSET; in cayman_dma_set_wptr()169 rb_cntl = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET); in cayman_dma_stop()171 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, rb_cntl); in cayman_dma_stop()200 reg_offset = DMA1_REGISTER_OFFSET; in cayman_dma_resume()
881 case (DMA_STATUS_REG + DMA1_REGISTER_OFFSET): in cayman_get_allowed_info_register()1143 WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config); in cayman_gpu_init()1783 tmp = RREG32(DMA_STATUS_REG + DMA1_REGISTER_OFFSET); in cayman_gpu_check_soft_reset()1866 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET); in cayman_gpu_soft_reset()1868 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp); in cayman_gpu_soft_reset()
1309 case (DMA_STATUS_REG + DMA1_REGISTER_OFFSET): in si_get_allowed_info_register()3269 WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config); in si_gpu_init()3793 tmp = RREG32(DMA_STATUS_REG + DMA1_REGISTER_OFFSET); in si_gpu_check_soft_reset()3876 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET); in si_gpu_soft_reset()3878 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp); in si_gpu_soft_reset()4041 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET); in si_gpu_pci_config_reset()4043 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp); in si_gpu_pci_config_reset()5527 offset = DMA1_REGISTER_OFFSET; in si_enable_dma_mgcg()5539 offset = DMA1_REGISTER_OFFSET; in si_enable_dma_mgcg()5946 tmp = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE; in si_disable_interrupt_state()[all …]
1302 #define DMA1_REGISTER_OFFSET 0x800 /* not a register */ macro
1813 #define DMA1_REGISTER_OFFSET 0x800 /* not a register */ macro