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Searched refs:DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK (Results 1 – 4 of 4) sorted by relevance

/dragonfly/sys/dev/drm/amd/amdgpu/
HDdf_v3_6.c85 tmp &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK; in df_v3_6_update_medium_grain_clock_gating()
92 tmp &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK; in df_v3_6_update_medium_grain_clock_gating()
HDdf_v1_7.c80 tmp &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK; in df_v1_7_update_medium_grain_clock_gating()
85 tmp &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK; in df_v1_7_update_medium_grain_clock_gating()
/dragonfly/sys/dev/drm/amd/include/asic_reg/df/
HDdf_3_6_sh_mask.h34 #define DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK … macro
HDdf_1_7_sh_mask.h34 #define DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK … macro