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Searched refs:DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT (Results 1 – 7 of 7) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/dce/
HDdce_6_0_sh_mask.h5226 #define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT 0x00000000 macro
HDdce_8_0_sh_mask.h2888 #define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT 0x0 macro
HDdce_10_0_sh_mask.h2686 #define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT 0x0 macro
HDdce_11_0_sh_mask.h2700 #define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT 0x0 macro
HDdce_11_2_sh_mask.h2940 #define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT 0x0 macro
HDdce_12_0_sh_mask.h9001 #define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT … macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/dcn/
HDdcn_1_0_sh_mask.h39747 #define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT … macro