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Searched refs:DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL_MASK (Results 1 – 7 of 7) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/dce/
HDdce_6_0_sh_mask.h5225 #define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL_MASK 0x00000003L macro
HDdce_8_0_sh_mask.h2887 #define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL_MASK 0x3 macro
HDdce_10_0_sh_mask.h2685 #define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL_MASK 0x3 macro
HDdce_11_0_sh_mask.h2699 #define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL_MASK 0x3 macro
HDdce_11_2_sh_mask.h2939 #define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL_MASK 0x3 macro
HDdce_12_0_sh_mask.h9003 #define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL_MASK … macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/dcn/
HDdcn_1_0_sh_mask.h39749 #define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL_MASK … macro