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Searched refs:DC_GPIO_DDCVGA_MASK__AUXVGA_POL_MASK (Results 1 – 7 of 7) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/dce/
HDdce_6_0_sh_mask.h3461 #define DC_GPIO_DDCVGA_MASK__AUXVGA_POL_MASK 0x00100000L macro
HDdce_8_0_sh_mask.h3867 #define DC_GPIO_DDCVGA_MASK__AUXVGA_POL_MASK 0x100000 macro
HDdce_10_0_sh_mask.h3771 #define DC_GPIO_DDCVGA_MASK__AUXVGA_POL_MASK 0x100000 macro
HDdce_11_0_sh_mask.h3859 #define DC_GPIO_DDCVGA_MASK__AUXVGA_POL_MASK 0x100000 macro
HDdce_11_2_sh_mask.h4241 #define DC_GPIO_DDCVGA_MASK__AUXVGA_POL_MASK 0x100000 macro
HDdce_12_0_sh_mask.h10236 #define DC_GPIO_DDCVGA_MASK__AUXVGA_POL_MASK … macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/dcn/
HDdcn_1_0_sh_mask.h40846 #define DC_GPIO_DDCVGA_MASK__AUXVGA_POL_MASK … macro