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Searched refs:DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM_MASK (Results 1 – 6 of 6) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
HDgfx_6_0_sh_mask.h3280 #define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM_MASK 0x00000010L macro
HDgfx_7_2_sh_mask.h3911 #define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM_MASK 0x10 macro
HDgfx_8_1_sh_mask.h5161 #define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM_MASK 0x10 macro
HDgfx_8_0_sh_mask.h4637 #define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM_MASK 0x10 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
HDgc_9_0_sh_mask.h4914 #define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM_MASK … macro
HDgc_9_2_1_sh_mask.h4314 #define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM_MASK … macro