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Searched refs:D5VGA_CONTROL__D5VGA_TIMING_SELECT_MASK (Results 1 – 7 of 7) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/dce/
HDdce_6_0_sh_mask.h2553 #define D5VGA_CONTROL__D5VGA_TIMING_SELECT_MASK 0x00000100L macro
HDdce_8_0_sh_mask.h11065 #define D5VGA_CONTROL__D5VGA_TIMING_SELECT_MASK 0x100 macro
HDdce_10_0_sh_mask.h11449 #define D5VGA_CONTROL__D5VGA_TIMING_SELECT_MASK 0x100 macro
HDdce_11_0_sh_mask.h11261 #define D5VGA_CONTROL__D5VGA_TIMING_SELECT_MASK 0x100 macro
HDdce_11_2_sh_mask.h12515 #define D5VGA_CONTROL__D5VGA_TIMING_SELECT_MASK 0x100 macro
HDdce_12_0_sh_mask.h2308 #define D5VGA_CONTROL__D5VGA_TIMING_SELECT_MASK … macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/dcn/
HDdcn_1_0_sh_mask.h1754 #define D5VGA_CONTROL__D5VGA_TIMING_SELECT_MASK … macro