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Searched refs:CURSOR0_CONTROL (Results 1 – 3 of 3) sorted by relevance

/dragonfly/sys/dev/drm/amd/display/dc/dcn10/
HDdcn10_ipp.h37 SRI(CURSOR0_CONTROL, CNVC_CUR, id), \
135 uint32_t CURSOR0_CONTROL; member
HDdcn10_dpp.c422 REG_UPDATE(CURSOR0_CONTROL, in dpp1_cnv_setup()
433 REG_UPDATE_2(CURSOR0_CONTROL, in dpp1_set_cursor_attributes()
463 REG_UPDATE(CURSOR0_CONTROL, in dpp1_set_cursor_position()
HDdcn10_dpp.h119 SRI(CURSOR0_CONTROL, CNVC_CUR, id), \
1333 uint32_t CURSOR0_CONTROL; \