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Searched refs:CSR_WRITE_1 (Results 1 – 25 of 35) sorted by relevance

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/dragonfly/sys/dev/netif/vge/
HDif_vge.c251 CSR_WRITE_1(sc, VGE_EEADDR, addr); in vge_eeprom_getword()
307 CSR_WRITE_1(sc, VGE_MIICMD, 0); in vge_miipoll_stop()
324 CSR_WRITE_1(sc, VGE_MIICMD, 0); in vge_miipoll_start()
325 CSR_WRITE_1(sc, VGE_MIIADDR, VGE_MIIADDR_SWMPL); in vge_miipoll_start()
338 CSR_WRITE_1(sc, VGE_MIICMD, VGE_MIICMD_MAUTO); in vge_miipoll_start()
365 CSR_WRITE_1(sc, VGE_MIIADDR, reg); in vge_miibus_readreg()
400 CSR_WRITE_1(sc, VGE_MIIADDR, reg); in vge_miibus_writereg()
436 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE); in vge_cam_clear()
438 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); in vge_cam_clear()
441 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|VGE_CAMADDR_AVSEL|0); in vge_cam_clear()
[all …]
HDif_vgevar.h140 #define CSR_WRITE_1(sc, reg, val) \ macro
151 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x))
158 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x))
/dragonfly/sys/dev/netif/msk/
HDif_msk.c469 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK), in msk_miibus_statchg()
1023 CSR_WRITE_1(sc, B0_POWER_CTRL, in mskc_phy_power()
1039 CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val); in mskc_phy_power()
1107 CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val); in mskc_phy_power()
1108 CSR_WRITE_1(sc, B0_POWER_CTRL, in mskc_phy_power()
1140 CSR_WRITE_1(sc, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET); in mskc_reset()
1153 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); in mskc_reset()
1190 CSR_WRITE_1(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_SET); in mskc_reset()
1191 CSR_WRITE_1(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_CLR); in mskc_reset()
1211 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); in mskc_reset()
[all …]
/dragonfly/sys/dev/netif/rl/
HDif_rl.c257 CSR_WRITE_1(sc, RL_EECMD, CSR_READ_1(sc, RL_EECMD) | (x))
260 CSR_WRITE_1(sc, RL_EECMD, CSR_READ_1(sc, RL_EECMD) & ~(x))
298 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); in rl_eeprom_getword()
305 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); in rl_eeprom_getword()
320 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); in rl_eeprom_getword()
352 CSR_WRITE_1(sc, RL_MII, CSR_READ_1(sc, RL_MII) | x)
355 CSR_WRITE_1(sc, RL_MII, CSR_READ_1(sc, RL_MII) & ~x)
694 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); in rl_reset()
1406 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); in rl_init()
1411 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); in rl_init()
[all …]
HDif_rlreg.h397 #define CSR_WRITE_1(sc, reg, val) \ macro
/dragonfly/sys/dev/netif/vr/
HDif_vr.c209 CSR_WRITE_1(sc, reg, \
213 CSR_WRITE_1(sc, reg, \
233 CSR_WRITE_1(sc, VR_MIICMD, \
237 CSR_WRITE_1(sc, VR_MIICMD, \
297 CSR_WRITE_1(sc, VR_MIICMD, 0); in vr_mii_readreg()
368 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)|
372 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr);
394 CSR_WRITE_1(sc, VR_MIICMD, 0); in vr_mii_writereg()
430 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)|
434 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr);
[all …]
HDif_vrreg.h487 #define CSR_WRITE_1(sc, reg, val) \ macro
/dragonfly/sys/dev/netif/re/
HDif_revar.h227 #define CSR_WRITE_1(sc, reg, val) \ macro
238 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (val))
240 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(val))
HDre.c144 CSR_WRITE_1(sc, RE_EECMD, \
148 CSR_WRITE_1(sc, RE_EECMD, \
609 CSR_WRITE_1(sc, RE_PMCH, CSR_READ_1(sc, RE_PMCH) | (BIT_6|BIT_7)); in re_phy_power_up()
744 CSR_WRITE_1(sc, 0xD0, CSR_READ_1(sc, 0xD0) & ~BIT_6); in re_phy_power_down()
764 CSR_WRITE_1(sc, 0xD0, CSR_READ_1(sc, 0xD0) & ~BIT_6); in re_phy_power_down()
765 CSR_WRITE_1(sc, 0xF2, CSR_READ_1(sc, 0xF2) & ~BIT_6); in re_phy_power_down()
770 CSR_WRITE_1(sc, RE_PMCH, CSR_READ_1(sc, RE_PMCH) & ~(BIT_6|BIT_7)); in re_phy_power_down()
1150 CSR_WRITE_1(sc, RE_CFG5, CSR_READ_1(sc, RE_CFG5) & ~BIT_0); in DisableMcuBPs()
1151 CSR_WRITE_1(sc, RE_CFG2, CSR_READ_1(sc, RE_CFG2) & ~BIT_7); in DisableMcuBPs()
3534 CSR_WRITE_1(sc, RE_MCU_CMD, CSR_READ_1(sc, RE_MCU_CMD) & ~RE_NOW_IS_OOB); in re_disable_now_is_oob()
[all …]
/dragonfly/sys/dev/netif/ste/
HDif_ste.c181 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | x)
184 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~x)
1133 CSR_WRITE_1(sc, STE_PAR0 + i, sc->arpcom.ac_enaddr[i]); in ste_init()
1145 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 1); in ste_init()
1151 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8); in ste_init()
1157 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4)); in ste_init()
1160 CSR_WRITE_1(sc, STE_RX_MODE, STE_RXMODE_UNICAST); in ste_init()
1187 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0); in ste_init()
1457 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64); in ste_start()
HDif_stereg.h437 #define CSR_WRITE_1(sc, reg, val) \ macro
/dragonfly/sys/dev/netif/stge/
HDif_stge.c219 CSR_WRITE_1(sc, STGE_PhyCtrl, CSR_READ_1(sc, STGE_PhyCtrl) | (x))
221 CSR_WRITE_1(sc, STGE_PhyCtrl, CSR_READ_1(sc, STGE_PhyCtrl) & ~(x))
279 CSR_WRITE_1(sc, STGE_PhyCtrl, 0 | sc->sc_PhyCtrl); in stge_mii_readreg()
1874 CSR_WRITE_1(sc, STGE_PhySet, v); in stge_reset()
1951 CSR_WRITE_1(sc, STGE_TxDMAPollPeriod, 127); in stge_init()
1954 CSR_WRITE_1(sc, STGE_RxDMAPollPeriod, 1); in stge_init()
1960 CSR_WRITE_1(sc, STGE_RxDMABurstThresh, 0x30); in stge_init()
1961 CSR_WRITE_1(sc, STGE_RxDMAUrgentThresh, 0x30); in stge_init()
1967 CSR_WRITE_1(sc, STGE_TxDMABurstThresh, 0x30); in stge_init()
1968 CSR_WRITE_1(sc, STGE_TxDMAUrgentThresh, 0x04); in stge_init()
[all …]
HDif_stgereg.h102 #define CSR_WRITE_1(_sc, reg, val) \ macro
/dragonfly/sys/dev/netif/fxp/
HDif_fxp.c321 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); in fxp_scb_cmd()
324 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); in fxp_scb_cmd()
745 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); in fxp_detach()
1213 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp); in fxp_npoll_compat()
1235 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, in fxp_npoll()
1243 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); in fxp_npoll()
1279 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); in fxp_intr()
1876 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); in fxp_init()
1880 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); in fxp_init()
HDif_fxpvar.h151 #define CSR_WRITE_1(sc, reg, val) \ macro
/dragonfly/sys/dev/netif/xl/
HDif_xl.c592 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX); in xl_miibus_statchg()
594 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, in xl_miibus_statchg()
909 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX); in xl_setmode()
913 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, in xl_setmode()
2186 CSR_WRITE_1(sc, XL_DOWN_POLL, 64); in xl_txeoc()
2197 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8); in xl_txeoc()
2221 CSR_WRITE_1(sc, XL_TX_STATUS, 0x01); in xl_txeoc()
2727 CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i, in xl_init()
2762 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8); in xl_init()
2819 CSR_WRITE_1(sc, XL_UP_POLL, 64); in xl_init()
[all …]
HDif_xlreg.h642 #define CSR_WRITE_1(sc, reg, val) \ macro
/dragonfly/sys/dev/netif/tx/
HDif_txvar.h110 #define CSR_WRITE_1(sc, reg, val) \ macro
/dragonfly/sys/dev/netif/iwi/
HDif_iwireg.h584 #define CSR_WRITE_1(sc, reg, val) \ macro
602 CSR_WRITE_1((sc), IWI_CSR_INDIRECT_DATA, (val)); \
/dragonfly/sys/dev/netif/ale/
HDif_alevar.h233 #define CSR_WRITE_1(_sc, reg, val) \ macro
/dragonfly/sys/dev/netif/wb/
HDif_wbreg.h390 #define CSR_WRITE_1(sc, reg, val) \ macro
/dragonfly/sys/dev/netif/my/
HDif_myreg.h384 #define CSR_WRITE_1(sc, reg, val) \ macro
/dragonfly/sys/dev/netif/tl/
HDif_tlreg.h495 #define CSR_WRITE_1(sc, reg, val) \ macro
/dragonfly/sys/dev/netif/lge/
HDif_lgereg.h556 #define CSR_WRITE_1(sc, reg, val) \ macro
/dragonfly/sys/dev/netif/wi/
HDif_wireg.h111 #define CSR_WRITE_1(sc, reg, val) \ macro

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