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Searched refs:CSR_READ_2 (Results 1 – 25 of 43) sorted by relevance

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/dragonfly/sys/dev/netif/vge/
HDif_vgevar.h145 #define CSR_READ_2(sc, reg) \ macro
153 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x))
160 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x))
/dragonfly/sys/dev/netif/stge/
HDif_stge.c522 if ((CSR_READ_2(sc, STGE_EepromCtrl) & EC_EepromBusy) == 0) in stge_eeprom_wait()
544 *data = CSR_READ_2(sc, STGE_EepromData); in stge_read_eeprom()
699 v = CSR_READ_2(sc, STGE_StationAddress0); in stge_attach()
702 v = CSR_READ_2(sc, STGE_StationAddress1); in stge_attach()
705 v = CSR_READ_2(sc, STGE_StationAddress2); in stge_attach()
1400 status = CSR_READ_2(sc, STGE_IntStatus); in stge_intr()
1406 status = CSR_READ_2(sc, STGE_IntStatusAck); in stge_intr()
1695 status = CSR_READ_2(sc, STGE_IntStatus); in stge_npoll_compat()
1793 IFNET_STAT_INC(ifp, ierrors, CSR_READ_2(sc, STGE_FramesLostRxErrors)); in stge_stats_update()
1805 CSR_READ_2(sc, STGE_FramesAbortXSColls) + in stge_stats_update()
[all …]
HDif_stgereg.h107 #define CSR_READ_2(_sc, reg) \ macro
/dragonfly/sys/dev/netif/ste/
HDif_ste.c175 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | x)
178 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~x)
277 ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA; in ste_mii_readreg()
299 if (CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA) in ste_mii_readreg()
491 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY) in ste_eeprom_wait()
523 word = CSR_READ_2(sc, STE_EEPROM_DATA); in ste_read_eeprom()
589 if (!(CSR_READ_2(sc, STE_ISR) & STE_ISR_INTLATCH)) in ste_intr()
593 status = CSR_READ_2(sc, STE_ISR_ACK); in ste_intr()
HDif_stereg.h442 #define CSR_READ_2(sc, reg) \ macro
/dragonfly/sys/dev/netif/wi/
HDif_wi_pci.c228 (CSR_READ_2(sc, WI_COMMAND) & WI_CMD_BUSY)) in wi_pci_attach()
239 reg = CSR_READ_2(sc, WI_HFA384X_SWSUPPORT0_OFF); in wi_pci_attach()
HDif_wi.c613 status = CSR_READ_2(sc, WI_EVENT_STAT); in wi_intr()
1290 fid = CSR_READ_2(sc, WI_RX_FID); in wi_rx_intr()
1406 fid = CSR_READ_2(sc, WI_TX_CMP_FID); in wi_tx_ex_intr()
1459 fid = CSR_READ_2(sc, WI_ALLOC_FID); in wi_tx_intr()
1492 fid = CSR_READ_2(sc, WI_INFO_FID); in wi_info_intr()
1820 if (!(CSR_READ_2(sc, WI_COMMAND) & WI_CMD_BUSY)) in wi_cmd()
1845 s = CSR_READ_2(sc, WI_EVENT_STAT); in wi_cmd()
1848 s = CSR_READ_2(sc, WI_STATUS); in wi_cmd()
1877 status = CSR_READ_2(sc, WI_OFF0); in wi_seek_bap()
1976 if (CSR_READ_2(sc, WI_EVENT_STAT) & WI_EV_ALLOC) in wi_alloc_fid()
[all …]
/dragonfly/sys/dev/netif/vr/
HDif_vr.c218 CSR_READ_2(sc, reg) | (x))
222 CSR_READ_2(sc, reg) & ~(x))
380 frame->mii_data = CSR_READ_2(sc, VR_MIIDATA);
579 if (CSR_READ_2(sc, VR_COMMAND) & (VR_CMD_TX_ON|VR_CMD_RX_ON)) { in vr_setcfg()
602 if (!(CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RESET)) in vr_reset()
1045 i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RX_ON); in vr_rxeoc()
1100 i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_TX_ON); in vr_txeof()
1203 status = CSR_READ_2(sc, VR_ISR); in vr_intr()
HDif_vrreg.h492 #define CSR_READ_2(sc, reg) \ macro
/dragonfly/sys/dev/netif/xl/
HDif_xl.c329 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY)) in xl_wait()
350 CSR_READ_2(sc, XL_W4_PHY_MGMT) | (x))
354 CSR_READ_2(sc, XL_W4_PHY_MGMT) & ~(x))
448 ack = CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA; in xl_mii_readreg()
466 if (CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA) in xl_mii_readreg()
658 if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY) in xl_eeprom_wait()
705 word = CSR_READ_2(sc, XL_W0_EE_DATA); in xl_read_eeprom()
845 mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); in xl_setmode()
950 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY)) in xl_reset()
973 CSR_WRITE_2(sc, XL_W2_RESET_OPTIONS, CSR_READ_2(sc, in xl_reset()
[all …]
/dragonfly/sys/dev/netif/rl/
HDif_rl.c442 ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN; in rl_mii_readreg()
462 if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN) in rl_mii_readreg()
567 rval = CSR_READ_2(sc, rl8139_reg); in rl_miibus_readreg()
996 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % in rl_rxeof()
1000 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN; in rl_rxeof()
1192 status = CSR_READ_2(sc, RL_ISR); in rl_npoll_compat()
1255 status = CSR_READ_2(sc, RL_ISR); in rl_intr()
HDif_rlreg.h402 #define CSR_READ_2(sc, reg) \ macro
/dragonfly/sys/dev/netif/fxp/
HDif_fxpvar.h147 #define CSR_READ_2(sc, reg) \ macro
/dragonfly/sys/dev/netif/tx/
HDif_txvar.h114 #define CSR_READ_2(sc, reg) \ macro
/dragonfly/sys/dev/netif/pcn/
HDif_pcn.c210 return(CSR_READ_2(sc, PCN_IO16_RDP)); in pcn_csr_read16()
232 return(CSR_READ_2(sc, PCN_IO16_BDP)); in pcn_bcr_read16()
362 CSR_READ_2(sc, PCN_IO16_RESET); in pcn_reset()
573 *(uint16_t *)(eaddr + 4) = CSR_READ_2(sc, PCN_IO32_APROM01); in pcn_attach()
HDif_pcnreg.h455 #define CSR_READ_2(sc, reg) \ macro
/dragonfly/sys/dev/netif/ale/
HDif_alevar.h235 #define CSR_READ_2(_sc, reg) \ macro
/dragonfly/sys/dev/netif/age/
HDif_agevar.h236 #define CSR_READ_2(_sc, reg) \ macro
/dragonfly/sys/dev/netif/alc/
HDif_alcvar.h264 #define CSR_READ_2(sc, reg) \ macro
/dragonfly/sys/dev/netif/re/
HDif_revar.h232 #define CSR_READ_2(sc, reg) \ macro
/dragonfly/sys/dev/netif/wb/
HDif_wbreg.h395 #define CSR_READ_2(sc, reg) \ macro
/dragonfly/sys/dev/netif/my/
HDif_myreg.h389 #define CSR_READ_2(sc, reg) \ macro
/dragonfly/sys/dev/netif/sis/
HDif_sisreg.h467 #define CSR_READ_2(sc, reg) \ macro
/dragonfly/sys/dev/netif/tl/
HDif_tl.c370 return(CSR_READ_2(sc, TL_DIO_DATA + (reg & 3))); in tl_dio_read16()
436 f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3)); in tl_dio_setbit16()
449 f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3)); in tl_dio_clrbit16()
1607 ints = CSR_READ_2(sc, TL_HOST_INT); in tl_intr()
HDif_tlreg.h500 #define CSR_READ_2(sc, reg) \ macro

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