Home
last modified time | relevance | path

Searched refs:CP_ROQ2_THRESHOLDS__R0_IB2_START__SHIFT (Results 1 – 6 of 6) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
HDgfx_6_0_sh_mask.h2879 #define CP_ROQ2_THRESHOLDS__R0_IB2_START__SHIFT 0x00000008 macro
HDgfx_7_2_sh_mask.h3136 #define CP_ROQ2_THRESHOLDS__R0_IB2_START__SHIFT 0x8 macro
HDgfx_8_1_sh_mask.h4272 #define CP_ROQ2_THRESHOLDS__R0_IB2_START__SHIFT 0x8 macro
HDgfx_8_0_sh_mask.h3750 #define CP_ROQ2_THRESHOLDS__R0_IB2_START__SHIFT 0x8 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
HDgc_9_0_sh_mask.h1133 #define CP_ROQ2_THRESHOLDS__R0_IB2_START__SHIFT … macro
HDgc_9_2_1_sh_mask.h1098 #define CP_ROQ2_THRESHOLDS__R0_IB2_START__SHIFT … macro