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Searched refs:CP_ROQ1_THRESHOLDS__R0_IB1_START_MASK (Results 1 – 6 of 6) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
HDgfx_6_0_sh_mask.h2868 #define CP_ROQ1_THRESHOLDS__R0_IB1_START_MASK 0x00ff0000L macro
HDgfx_7_2_sh_mask.h3129 #define CP_ROQ1_THRESHOLDS__R0_IB1_START_MASK 0xff0000 macro
HDgfx_8_1_sh_mask.h4265 #define CP_ROQ1_THRESHOLDS__R0_IB1_START_MASK 0xff0000 macro
HDgfx_8_0_sh_mask.h3743 #define CP_ROQ1_THRESHOLDS__R0_IB1_START_MASK 0xff0000 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
HDgc_9_0_sh_mask.h1129 #define CP_ROQ1_THRESHOLDS__R0_IB1_START_MASK … macro
HDgc_9_2_1_sh_mask.h1094 #define CP_ROQ1_THRESHOLDS__R0_IB1_START_MASK … macro