CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT (reference) in projects: dragonfly

Searched refs:CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT (Results 1 – 7 of 7) sorted by relevance

/dragonfly/sys/dev/drm/amd/amdgpu/
H D	gfx_v9_0.c	`2051 data \|= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); in gfx_v9_0_init_gfx_power_gating() 3648 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); in gfx_v9_0_update_3d_clock_gating() 3698 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); in gfx_v9_0_update_coarse_grain_clock_gating()`
/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
H D	gfx_6_0_sh_mask.h	`2847 #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x00000010 macro`
H D	gfx_7_2_sh_mask.h	`3082 #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 macro`
H D	gfx_8_1_sh_mask.h	`4218 #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 macro`
H D	gfx_8_0_sh_mask.h	`3696 #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 macro`
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
H D	gc_9_0_sh_mask.h	`1119 #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT … macro`
H D	gc_9_2_1_sh_mask.h	`1084 #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT … macro`