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Searched refs:CP_RB0_CNTL__CACHE_POLICY__SHIFT (Results 1 – 6 of 6) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
HDgfx_6_0_sh_mask.h2713 #define CP_RB0_CNTL__CACHE_POLICY__SHIFT 0x00000018 macro
HDgfx_7_2_sh_mask.h1052 #define CP_RB0_CNTL__CACHE_POLICY__SHIFT 0x18 macro
HDgfx_8_1_sh_mask.h1894 #define CP_RB0_CNTL__CACHE_POLICY__SHIFT 0x18 macro
HDgfx_8_0_sh_mask.h1370 #define CP_RB0_CNTL__CACHE_POLICY__SHIFT 0x18 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
HDgc_9_0_sh_mask.h10570 #define CP_RB0_CNTL__CACHE_POLICY__SHIFT … macro
HDgc_9_2_1_sh_mask.h11981 #define CP_RB0_CNTL__CACHE_POLICY__SHIFT … macro