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Searched refs:CP_QUEUE_THRESHOLDS__ROQ_IB2_START_MASK (Results 1 – 6 of 6) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
HDgfx_6_0_sh_mask.h2704 #define CP_QUEUE_THRESHOLDS__ROQ_IB2_START_MASK 0x00003f00L macro
HDgfx_7_2_sh_mask.h3149 #define CP_QUEUE_THRESHOLDS__ROQ_IB2_START_MASK 0x3f00 macro
HDgfx_8_1_sh_mask.h4285 #define CP_QUEUE_THRESHOLDS__ROQ_IB2_START_MASK 0x3f00 macro
HDgfx_8_0_sh_mask.h3763 #define CP_QUEUE_THRESHOLDS__ROQ_IB2_START_MASK 0x3f00 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
HDgc_9_0_sh_mask.h1151 #define CP_QUEUE_THRESHOLDS__ROQ_IB2_START_MASK … macro
HDgc_9_2_1_sh_mask.h1116 #define CP_QUEUE_THRESHOLDS__ROQ_IB2_START_MASK … macro