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Searched refs:CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN__SHIFT (Results 1 – 6 of 6) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
HDgfx_6_0_sh_mask.h2687 #define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN__SHIFT 0x00000010 macro
HDgfx_7_2_sh_mask.h2778 #define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN__SHIFT 0x10 macro
HDgfx_8_1_sh_mask.h3868 #define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN__SHIFT 0x10 macro
HDgfx_8_0_sh_mask.h3346 #define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN__SHIFT 0x10 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
HDgc_9_0_sh_mask.h19433 #define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN__SHIFT … macro
HDgc_9_2_1_sh_mask.h20796 #define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN__SHIFT … macro