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Searched refs:CP_ME_CNTL__PFP_HALT_MASK (Results 1 – 6 of 6) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
HDgfx_6_0_sh_mask.h2572 #define CP_ME_CNTL__PFP_HALT_MASK 0x04000000L macro
HDgfx_7_2_sh_mask.h3049 #define CP_ME_CNTL__PFP_HALT_MASK 0x4000000 macro
HDgfx_8_1_sh_mask.h4185 #define CP_ME_CNTL__PFP_HALT_MASK 0x4000000 macro
HDgfx_8_0_sh_mask.h3663 #define CP_ME_CNTL__PFP_HALT_MASK 0x4000000 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
HDgc_9_0_sh_mask.h1076 #define CP_ME_CNTL__PFP_HALT_MASK … macro
HDgc_9_2_1_sh_mask.h1041 #define CP_ME_CNTL__PFP_HALT_MASK … macro