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Searched refs:CP_MEC_CNTL__MEC_ME1_HALT_MASK (Results 1 – 7 of 7) sorted by relevance

/dragonfly/sys/dev/drm/amd/amdgpu/
HDgfx_v9_0.c2530 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK)); in gfx_v9_0_cp_compute_enable()
HDgfx_v8_0.c4535 … WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK)); in gfx_v8_0_cp_compute_enable()
/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
HDgfx_7_2_sh_mask.h2225 #define CP_MEC_CNTL__MEC_ME1_HALT_MASK 0x40000000 macro
HDgfx_8_1_sh_mask.h3293 #define CP_MEC_CNTL__MEC_ME1_HALT_MASK 0x40000000 macro
HDgfx_8_0_sh_mask.h2771 #define CP_MEC_CNTL__MEC_ME1_HALT_MASK 0x40000000 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
HDgc_9_0_sh_mask.h749 #define CP_MEC_CNTL__MEC_ME1_HALT_MASK … macro
HDgc_9_2_1_sh_mask.h736 #define CP_MEC_CNTL__MEC_ME1_HALT_MASK … macro