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Searched refs:CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT (Results 1 – 4 of 4) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
HDgfx_8_1_sh_mask.h2374 #define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT 0x6 macro
HDgfx_8_0_sh_mask.h1850 #define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT 0x6 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
HDgc_9_0_sh_mask.h11868 #define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT … macro
HDgc_9_2_1_sh_mask.h13183 #define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT … macro