Home
last modified time | relevance | path

Searched refs:CP_ME2_PIPE1_INT_CNTL (Results 1 – 3 of 3) sorted by relevance

/dragonfly/sys/dev/drm/radeon/
HDcikd.h1363 #define CP_ME2_PIPE1_INT_CNTL 0xC228 macro
HDcik.c6921 WREG32(CP_ME2_PIPE1_INT_CNTL, 0); in cik_disable_interrupt_state()
/dragonfly/sys/dev/drm/amd/amdgpu/
HDgfx_v8_0.c6902 WREG32_FIELD(CP_ME2_PIPE1_INT_CNTL, CP_ECC_ERROR_INT_ENABLE, in gfx_v8_0_set_cp_ecc_int_state()