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Searched refs:CP_INT_STATUS_RING2__GENERIC1_INT_STAT_MASK (Results 1 – 6 of 6) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
HDgfx_6_0_sh_mask.h2538 #define CP_INT_STATUS_RING2__GENERIC1_INT_STAT_MASK 0x40000000L macro
HDgfx_7_2_sh_mask.h1335 #define CP_INT_STATUS_RING2__GENERIC1_INT_STAT_MASK 0x40000000 macro
HDgfx_8_1_sh_mask.h2223 #define CP_INT_STATUS_RING2__GENERIC1_INT_STAT_MASK 0x40000000 macro
HDgfx_8_0_sh_mask.h1699 #define CP_INT_STATUS_RING2__GENERIC1_INT_STAT_MASK 0x40000000 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
HDgc_9_0_sh_mask.h11051 #define CP_INT_STATUS_RING2__GENERIC1_INT_STAT_MASK macro
HDgc_9_2_1_sh_mask.h12461 #define CP_INT_STATUS_RING2__GENERIC1_INT_STAT_MASK macro