Home
last modified time | relevance | path

Searched refs:CP_INT_CNTL__PRIV_REG_INT_ENABLE_MASK (Results 1 – 6 of 6) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
HDgfx_6_0_sh_mask.h2358 #define CP_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L macro
HDgfx_7_2_sh_mask.h1157 #define CP_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000 macro
HDgfx_8_1_sh_mask.h2003 #define CP_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000 macro
HDgfx_8_0_sh_mask.h1479 #define CP_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
HDgc_9_0_sh_mask.h10650 #define CP_INT_CNTL__PRIV_REG_INT_ENABLE_MASK … macro
HDgc_9_2_1_sh_mask.h12060 #define CP_INT_CNTL__PRIV_REG_INT_ENABLE_MASK … macro