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Searched refs:CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE_MASK (Results 1 – 6 of 6) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
HDgfx_6_0_sh_mask.h2422 #define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L macro
HDgfx_7_2_sh_mask.h1231 #define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 macro
HDgfx_8_1_sh_mask.h2095 #define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 macro
HDgfx_8_0_sh_mask.h1571 #define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
HDgc_9_0_sh_mask.h10948 #define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE_MASK … macro
HDgc_9_2_1_sh_mask.h12358 #define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE_MASK … macro