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Searched refs:CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE_MASK (Results 1 – 6 of 6) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
HDgfx_6_0_sh_mask.h2388 #define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L macro
HDgfx_7_2_sh_mask.h1201 #define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE_MASK 0x100000 macro
HDgfx_8_1_sh_mask.h2057 #define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE_MASK 0x100000 macro
HDgfx_8_0_sh_mask.h1533 #define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE_MASK 0x100000 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
HDgc_9_0_sh_mask.h10911 #define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE_MASK … macro
HDgc_9_2_1_sh_mask.h12321 #define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE_MASK … macro