Home
last modified time | relevance | path

Searched refs:CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK (Results 1 – 9 of 9) sorted by relevance

/dragonfly/sys/dev/drm/amd/amdgpu/
HDamdgpu_amdkfd_gfx_v8.c284 WREG32(mmCPC_INT_CNTL, CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK); in kgd_init_interrupts()
HDamdgpu_amdkfd_gfx_v9.c362 CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK | in kgd_init_interrupts()
HDgfx_v8_0.c6793 mec_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; in gfx_v8_0_set_compute_eop_interrupt_state()
6798 mec_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; in gfx_v8_0_set_compute_eop_interrupt_state()
/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
HDgfx_6_0_sh_mask.h2382 #define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK 0x04000000L macro
HDgfx_7_2_sh_mask.h1185 #define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK 0x4000000 macro
HDgfx_8_1_sh_mask.h2037 #define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK 0x4000000 macro
HDgfx_8_0_sh_mask.h1513 #define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK 0x4000000 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
HDgc_9_0_sh_mask.h10883 #define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK … macro
HDgc_9_2_1_sh_mask.h12293 #define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK … macro