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Searched refs:CP_HQD_SEMA_CMD__RESULT__SHIFT (Results 1 – 5 of 5) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
HDgfx_7_2_sh_mask.h3414 #define CP_HQD_SEMA_CMD__RESULT__SHIFT 0x1 macro
HDgfx_8_1_sh_mask.h4570 #define CP_HQD_SEMA_CMD__RESULT__SHIFT 0x1 macro
HDgfx_8_0_sh_mask.h4048 #define CP_HQD_SEMA_CMD__RESULT__SHIFT 0x1 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
HDgc_9_0_sh_mask.h12876 #define CP_HQD_SEMA_CMD__RESULT__SHIFT … macro
HDgc_9_2_1_sh_mask.h14170 #define CP_HQD_SEMA_CMD__RESULT__SHIFT … macro