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Searched refs:CP_HQD_EOP_WPTR_MEM__WPTR__SHIFT (Results 1 – 4 of 4) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
HDgfx_8_1_sh_mask.h4688 #define CP_HQD_EOP_WPTR_MEM__WPTR__SHIFT 0x0 macro
HDgfx_8_0_sh_mask.h4166 #define CP_HQD_EOP_WPTR_MEM__WPTR__SHIFT 0x0 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
HDgc_9_0_sh_mask.h13059 #define CP_HQD_EOP_WPTR_MEM__WPTR__SHIFT … macro
HDgc_9_2_1_sh_mask.h14351 #define CP_HQD_EOP_WPTR_MEM__WPTR__SHIFT … macro