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Searched refs:CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY_MASK (Results 1 – 5 of 5) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
HDgfx_7_2_sh_mask.h2033 #define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY_MASK 0x400 macro
HDgfx_8_1_sh_mask.h3087 #define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY_MASK 0x400 macro
HDgfx_8_0_sh_mask.h2565 #define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY_MASK 0x400 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
HDgc_9_0_sh_mask.h549 #define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY_MASK … macro
HDgc_9_2_1_sh_mask.h536 #define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY_MASK … macro