1 /*
2 * Copyright 2004 ATI Technologies Inc., Markham, Ontario
3 * Copyright 2007-8 Advanced Micro Devices, Inc.
4 * Copyright 2008 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 */
27 #include <drm/drmP.h>
28 #include <drm/radeon_drm.h>
29 #include "radeon.h"
30 #include "atom.h"
31
32 #ifdef CONFIG_PPC_PMAC
33 /* not sure which of these are needed */
34 #include <asm/machdep.h>
35 #include <asm/pmac_feature.h>
36 #include <asm/prom.h>
37 #endif /* CONFIG_PPC_PMAC */
38
39 /* old legacy ATI BIOS routines */
40
41 /* COMBIOS table offsets */
42 enum radeon_combios_table_offset {
43 /* absolute offset tables */
44 COMBIOS_ASIC_INIT_1_TABLE,
45 COMBIOS_BIOS_SUPPORT_TABLE,
46 COMBIOS_DAC_PROGRAMMING_TABLE,
47 COMBIOS_MAX_COLOR_DEPTH_TABLE,
48 COMBIOS_CRTC_INFO_TABLE,
49 COMBIOS_PLL_INFO_TABLE,
50 COMBIOS_TV_INFO_TABLE,
51 COMBIOS_DFP_INFO_TABLE,
52 COMBIOS_HW_CONFIG_INFO_TABLE,
53 COMBIOS_MULTIMEDIA_INFO_TABLE,
54 COMBIOS_TV_STD_PATCH_TABLE,
55 COMBIOS_LCD_INFO_TABLE,
56 COMBIOS_MOBILE_INFO_TABLE,
57 COMBIOS_PLL_INIT_TABLE,
58 COMBIOS_MEM_CONFIG_TABLE,
59 COMBIOS_SAVE_MASK_TABLE,
60 COMBIOS_HARDCODED_EDID_TABLE,
61 COMBIOS_ASIC_INIT_2_TABLE,
62 COMBIOS_CONNECTOR_INFO_TABLE,
63 COMBIOS_DYN_CLK_1_TABLE,
64 COMBIOS_RESERVED_MEM_TABLE,
65 COMBIOS_EXT_TMDS_INFO_TABLE,
66 COMBIOS_MEM_CLK_INFO_TABLE,
67 COMBIOS_EXT_DAC_INFO_TABLE,
68 COMBIOS_MISC_INFO_TABLE,
69 COMBIOS_CRT_INFO_TABLE,
70 COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE,
71 COMBIOS_COMPONENT_VIDEO_INFO_TABLE,
72 COMBIOS_FAN_SPEED_INFO_TABLE,
73 COMBIOS_OVERDRIVE_INFO_TABLE,
74 COMBIOS_OEM_INFO_TABLE,
75 COMBIOS_DYN_CLK_2_TABLE,
76 COMBIOS_POWER_CONNECTOR_INFO_TABLE,
77 COMBIOS_I2C_INFO_TABLE,
78 /* relative offset tables */
79 COMBIOS_ASIC_INIT_3_TABLE, /* offset from misc info */
80 COMBIOS_ASIC_INIT_4_TABLE, /* offset from misc info */
81 COMBIOS_DETECTED_MEM_TABLE, /* offset from misc info */
82 COMBIOS_ASIC_INIT_5_TABLE, /* offset from misc info */
83 COMBIOS_RAM_RESET_TABLE, /* offset from mem config */
84 COMBIOS_POWERPLAY_INFO_TABLE, /* offset from mobile info */
85 COMBIOS_GPIO_INFO_TABLE, /* offset from mobile info */
86 COMBIOS_LCD_DDC_INFO_TABLE, /* offset from mobile info */
87 COMBIOS_TMDS_POWER_TABLE, /* offset from mobile info */
88 COMBIOS_TMDS_POWER_ON_TABLE, /* offset from tmds power */
89 COMBIOS_TMDS_POWER_OFF_TABLE, /* offset from tmds power */
90 };
91
92 enum radeon_combios_ddc {
93 DDC_NONE_DETECTED,
94 DDC_MONID,
95 DDC_DVI,
96 DDC_VGA,
97 DDC_CRT2,
98 DDC_LCD,
99 DDC_GPIO,
100 };
101
102 enum radeon_combios_connector {
103 CONNECTOR_NONE_LEGACY,
104 CONNECTOR_PROPRIETARY_LEGACY,
105 CONNECTOR_CRT_LEGACY,
106 CONNECTOR_DVI_I_LEGACY,
107 CONNECTOR_DVI_D_LEGACY,
108 CONNECTOR_CTV_LEGACY,
109 CONNECTOR_STV_LEGACY,
110 CONNECTOR_UNSUPPORTED_LEGACY
111 };
112
113 static const int legacy_connector_convert[] = {
114 DRM_MODE_CONNECTOR_Unknown,
115 DRM_MODE_CONNECTOR_DVID,
116 DRM_MODE_CONNECTOR_VGA,
117 DRM_MODE_CONNECTOR_DVII,
118 DRM_MODE_CONNECTOR_DVID,
119 DRM_MODE_CONNECTOR_Composite,
120 DRM_MODE_CONNECTOR_SVIDEO,
121 DRM_MODE_CONNECTOR_Unknown,
122 };
123
combios_get_table_offset(struct drm_device * dev,enum radeon_combios_table_offset table)124 static uint16_t combios_get_table_offset(struct drm_device *dev,
125 enum radeon_combios_table_offset table)
126 {
127 struct radeon_device *rdev = dev->dev_private;
128 int rev, size;
129 uint16_t offset = 0, check_offset;
130
131 if (!rdev->bios)
132 return 0;
133
134 switch (table) {
135 /* absolute offset tables */
136 case COMBIOS_ASIC_INIT_1_TABLE:
137 check_offset = 0xc;
138 break;
139 case COMBIOS_BIOS_SUPPORT_TABLE:
140 check_offset = 0x14;
141 break;
142 case COMBIOS_DAC_PROGRAMMING_TABLE:
143 check_offset = 0x2a;
144 break;
145 case COMBIOS_MAX_COLOR_DEPTH_TABLE:
146 check_offset = 0x2c;
147 break;
148 case COMBIOS_CRTC_INFO_TABLE:
149 check_offset = 0x2e;
150 break;
151 case COMBIOS_PLL_INFO_TABLE:
152 check_offset = 0x30;
153 break;
154 case COMBIOS_TV_INFO_TABLE:
155 check_offset = 0x32;
156 break;
157 case COMBIOS_DFP_INFO_TABLE:
158 check_offset = 0x34;
159 break;
160 case COMBIOS_HW_CONFIG_INFO_TABLE:
161 check_offset = 0x36;
162 break;
163 case COMBIOS_MULTIMEDIA_INFO_TABLE:
164 check_offset = 0x38;
165 break;
166 case COMBIOS_TV_STD_PATCH_TABLE:
167 check_offset = 0x3e;
168 break;
169 case COMBIOS_LCD_INFO_TABLE:
170 check_offset = 0x40;
171 break;
172 case COMBIOS_MOBILE_INFO_TABLE:
173 check_offset = 0x42;
174 break;
175 case COMBIOS_PLL_INIT_TABLE:
176 check_offset = 0x46;
177 break;
178 case COMBIOS_MEM_CONFIG_TABLE:
179 check_offset = 0x48;
180 break;
181 case COMBIOS_SAVE_MASK_TABLE:
182 check_offset = 0x4a;
183 break;
184 case COMBIOS_HARDCODED_EDID_TABLE:
185 check_offset = 0x4c;
186 break;
187 case COMBIOS_ASIC_INIT_2_TABLE:
188 check_offset = 0x4e;
189 break;
190 case COMBIOS_CONNECTOR_INFO_TABLE:
191 check_offset = 0x50;
192 break;
193 case COMBIOS_DYN_CLK_1_TABLE:
194 check_offset = 0x52;
195 break;
196 case COMBIOS_RESERVED_MEM_TABLE:
197 check_offset = 0x54;
198 break;
199 case COMBIOS_EXT_TMDS_INFO_TABLE:
200 check_offset = 0x58;
201 break;
202 case COMBIOS_MEM_CLK_INFO_TABLE:
203 check_offset = 0x5a;
204 break;
205 case COMBIOS_EXT_DAC_INFO_TABLE:
206 check_offset = 0x5c;
207 break;
208 case COMBIOS_MISC_INFO_TABLE:
209 check_offset = 0x5e;
210 break;
211 case COMBIOS_CRT_INFO_TABLE:
212 check_offset = 0x60;
213 break;
214 case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE:
215 check_offset = 0x62;
216 break;
217 case COMBIOS_COMPONENT_VIDEO_INFO_TABLE:
218 check_offset = 0x64;
219 break;
220 case COMBIOS_FAN_SPEED_INFO_TABLE:
221 check_offset = 0x66;
222 break;
223 case COMBIOS_OVERDRIVE_INFO_TABLE:
224 check_offset = 0x68;
225 break;
226 case COMBIOS_OEM_INFO_TABLE:
227 check_offset = 0x6a;
228 break;
229 case COMBIOS_DYN_CLK_2_TABLE:
230 check_offset = 0x6c;
231 break;
232 case COMBIOS_POWER_CONNECTOR_INFO_TABLE:
233 check_offset = 0x6e;
234 break;
235 case COMBIOS_I2C_INFO_TABLE:
236 check_offset = 0x70;
237 break;
238 /* relative offset tables */
239 case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */
240 check_offset =
241 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
242 if (check_offset) {
243 rev = RBIOS8(check_offset);
244 if (rev > 0) {
245 check_offset = RBIOS16(check_offset + 0x3);
246 if (check_offset)
247 offset = check_offset;
248 }
249 }
250 break;
251 case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */
252 check_offset =
253 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
254 if (check_offset) {
255 rev = RBIOS8(check_offset);
256 if (rev > 0) {
257 check_offset = RBIOS16(check_offset + 0x5);
258 if (check_offset)
259 offset = check_offset;
260 }
261 }
262 break;
263 case COMBIOS_DETECTED_MEM_TABLE: /* offset from misc info */
264 check_offset =
265 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
266 if (check_offset) {
267 rev = RBIOS8(check_offset);
268 if (rev > 0) {
269 check_offset = RBIOS16(check_offset + 0x7);
270 if (check_offset)
271 offset = check_offset;
272 }
273 }
274 break;
275 case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */
276 check_offset =
277 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
278 if (check_offset) {
279 rev = RBIOS8(check_offset);
280 if (rev == 2) {
281 check_offset = RBIOS16(check_offset + 0x9);
282 if (check_offset)
283 offset = check_offset;
284 }
285 }
286 break;
287 case COMBIOS_RAM_RESET_TABLE: /* offset from mem config */
288 check_offset =
289 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
290 if (check_offset) {
291 while (RBIOS8(check_offset++));
292 check_offset += 2;
293 if (check_offset)
294 offset = check_offset;
295 }
296 break;
297 case COMBIOS_POWERPLAY_INFO_TABLE: /* offset from mobile info */
298 check_offset =
299 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
300 if (check_offset) {
301 check_offset = RBIOS16(check_offset + 0x11);
302 if (check_offset)
303 offset = check_offset;
304 }
305 break;
306 case COMBIOS_GPIO_INFO_TABLE: /* offset from mobile info */
307 check_offset =
308 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
309 if (check_offset) {
310 check_offset = RBIOS16(check_offset + 0x13);
311 if (check_offset)
312 offset = check_offset;
313 }
314 break;
315 case COMBIOS_LCD_DDC_INFO_TABLE: /* offset from mobile info */
316 check_offset =
317 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
318 if (check_offset) {
319 check_offset = RBIOS16(check_offset + 0x15);
320 if (check_offset)
321 offset = check_offset;
322 }
323 break;
324 case COMBIOS_TMDS_POWER_TABLE: /* offset from mobile info */
325 check_offset =
326 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
327 if (check_offset) {
328 check_offset = RBIOS16(check_offset + 0x17);
329 if (check_offset)
330 offset = check_offset;
331 }
332 break;
333 case COMBIOS_TMDS_POWER_ON_TABLE: /* offset from tmds power */
334 check_offset =
335 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
336 if (check_offset) {
337 check_offset = RBIOS16(check_offset + 0x2);
338 if (check_offset)
339 offset = check_offset;
340 }
341 break;
342 case COMBIOS_TMDS_POWER_OFF_TABLE: /* offset from tmds power */
343 check_offset =
344 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
345 if (check_offset) {
346 check_offset = RBIOS16(check_offset + 0x4);
347 if (check_offset)
348 offset = check_offset;
349 }
350 break;
351 default:
352 check_offset = 0;
353 break;
354 }
355
356 size = RBIOS8(rdev->bios_header_start + 0x6);
357 /* check absolute offset tables */
358 if (table < COMBIOS_ASIC_INIT_3_TABLE && check_offset && check_offset < size)
359 offset = RBIOS16(rdev->bios_header_start + check_offset);
360
361 return offset;
362 }
363
radeon_combios_check_hardcoded_edid(struct radeon_device * rdev)364 bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev)
365 {
366 int edid_info, size;
367 struct edid *edid;
368 unsigned char *raw;
369 edid_info = combios_get_table_offset(rdev->ddev, COMBIOS_HARDCODED_EDID_TABLE);
370 if (!edid_info)
371 return false;
372
373 raw = rdev->bios + edid_info;
374 size = EDID_LENGTH * (raw[0x7e] + 1);
375 edid = kmalloc(size, M_DRM, M_WAITOK);
376 if (edid == NULL)
377 return false;
378
379 memcpy((unsigned char *)edid, raw, size);
380
381 if (!drm_edid_is_valid(edid)) {
382 kfree(edid);
383 return false;
384 }
385
386 rdev->mode_info.bios_hardcoded_edid = edid;
387 rdev->mode_info.bios_hardcoded_edid_size = size;
388 return true;
389 }
390
391 /* this is used for atom LCDs as well */
392 struct edid *
radeon_bios_get_hardcoded_edid(struct radeon_device * rdev)393 radeon_bios_get_hardcoded_edid(struct radeon_device *rdev)
394 {
395 struct edid *edid;
396
397 if (rdev->mode_info.bios_hardcoded_edid) {
398 edid = kmalloc(rdev->mode_info.bios_hardcoded_edid_size,
399 M_DRM, M_WAITOK);
400 if (edid) {
401 memcpy((unsigned char *)edid,
402 (unsigned char *)rdev->mode_info.bios_hardcoded_edid,
403 rdev->mode_info.bios_hardcoded_edid_size);
404 return edid;
405 }
406 }
407 return NULL;
408 }
409
combios_setup_i2c_bus(struct radeon_device * rdev,enum radeon_combios_ddc ddc,u32 clk_mask,u32 data_mask)410 static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev,
411 enum radeon_combios_ddc ddc,
412 u32 clk_mask,
413 u32 data_mask)
414 {
415 struct radeon_i2c_bus_rec i2c;
416 int ddc_line = 0;
417
418 /* ddc id = mask reg
419 * DDC_NONE_DETECTED = none
420 * DDC_DVI = RADEON_GPIO_DVI_DDC
421 * DDC_VGA = RADEON_GPIO_VGA_DDC
422 * DDC_LCD = RADEON_GPIOPAD_MASK
423 * DDC_GPIO = RADEON_MDGPIO_MASK
424 * r1xx
425 * DDC_MONID = RADEON_GPIO_MONID
426 * DDC_CRT2 = RADEON_GPIO_CRT2_DDC
427 * r200
428 * DDC_MONID = RADEON_GPIO_MONID
429 * DDC_CRT2 = RADEON_GPIO_DVI_DDC
430 * r300/r350
431 * DDC_MONID = RADEON_GPIO_DVI_DDC
432 * DDC_CRT2 = RADEON_GPIO_DVI_DDC
433 * rv2xx/rv3xx
434 * DDC_MONID = RADEON_GPIO_MONID
435 * DDC_CRT2 = RADEON_GPIO_MONID
436 * rs3xx/rs4xx
437 * DDC_MONID = RADEON_GPIOPAD_MASK
438 * DDC_CRT2 = RADEON_GPIO_MONID
439 */
440 switch (ddc) {
441 case DDC_NONE_DETECTED:
442 default:
443 ddc_line = 0;
444 break;
445 case DDC_DVI:
446 ddc_line = RADEON_GPIO_DVI_DDC;
447 break;
448 case DDC_VGA:
449 ddc_line = RADEON_GPIO_VGA_DDC;
450 break;
451 case DDC_LCD:
452 ddc_line = RADEON_GPIOPAD_MASK;
453 break;
454 case DDC_GPIO:
455 ddc_line = RADEON_MDGPIO_MASK;
456 break;
457 case DDC_MONID:
458 if (rdev->family == CHIP_RS300 ||
459 rdev->family == CHIP_RS400 ||
460 rdev->family == CHIP_RS480)
461 ddc_line = RADEON_GPIOPAD_MASK;
462 else if (rdev->family == CHIP_R300 ||
463 rdev->family == CHIP_R350) {
464 ddc_line = RADEON_GPIO_DVI_DDC;
465 ddc = DDC_DVI;
466 } else
467 ddc_line = RADEON_GPIO_MONID;
468 break;
469 case DDC_CRT2:
470 if (rdev->family == CHIP_R200 ||
471 rdev->family == CHIP_R300 ||
472 rdev->family == CHIP_R350) {
473 ddc_line = RADEON_GPIO_DVI_DDC;
474 ddc = DDC_DVI;
475 } else if (rdev->family == CHIP_RS300 ||
476 rdev->family == CHIP_RS400 ||
477 rdev->family == CHIP_RS480)
478 ddc_line = RADEON_GPIO_MONID;
479 else if (rdev->family >= CHIP_RV350) {
480 ddc_line = RADEON_GPIO_MONID;
481 ddc = DDC_MONID;
482 } else
483 ddc_line = RADEON_GPIO_CRT2_DDC;
484 break;
485 }
486
487 if (ddc_line == RADEON_GPIOPAD_MASK) {
488 i2c.mask_clk_reg = RADEON_GPIOPAD_MASK;
489 i2c.mask_data_reg = RADEON_GPIOPAD_MASK;
490 i2c.a_clk_reg = RADEON_GPIOPAD_A;
491 i2c.a_data_reg = RADEON_GPIOPAD_A;
492 i2c.en_clk_reg = RADEON_GPIOPAD_EN;
493 i2c.en_data_reg = RADEON_GPIOPAD_EN;
494 i2c.y_clk_reg = RADEON_GPIOPAD_Y;
495 i2c.y_data_reg = RADEON_GPIOPAD_Y;
496 } else if (ddc_line == RADEON_MDGPIO_MASK) {
497 i2c.mask_clk_reg = RADEON_MDGPIO_MASK;
498 i2c.mask_data_reg = RADEON_MDGPIO_MASK;
499 i2c.a_clk_reg = RADEON_MDGPIO_A;
500 i2c.a_data_reg = RADEON_MDGPIO_A;
501 i2c.en_clk_reg = RADEON_MDGPIO_EN;
502 i2c.en_data_reg = RADEON_MDGPIO_EN;
503 i2c.y_clk_reg = RADEON_MDGPIO_Y;
504 i2c.y_data_reg = RADEON_MDGPIO_Y;
505 } else {
506 i2c.mask_clk_reg = ddc_line;
507 i2c.mask_data_reg = ddc_line;
508 i2c.a_clk_reg = ddc_line;
509 i2c.a_data_reg = ddc_line;
510 i2c.en_clk_reg = ddc_line;
511 i2c.en_data_reg = ddc_line;
512 i2c.y_clk_reg = ddc_line;
513 i2c.y_data_reg = ddc_line;
514 }
515
516 if (clk_mask && data_mask) {
517 /* system specific masks */
518 i2c.mask_clk_mask = clk_mask;
519 i2c.mask_data_mask = data_mask;
520 i2c.a_clk_mask = clk_mask;
521 i2c.a_data_mask = data_mask;
522 i2c.en_clk_mask = clk_mask;
523 i2c.en_data_mask = data_mask;
524 i2c.y_clk_mask = clk_mask;
525 i2c.y_data_mask = data_mask;
526 } else if ((ddc_line == RADEON_GPIOPAD_MASK) ||
527 (ddc_line == RADEON_MDGPIO_MASK)) {
528 /* default gpiopad masks */
529 i2c.mask_clk_mask = (0x20 << 8);
530 i2c.mask_data_mask = 0x80;
531 i2c.a_clk_mask = (0x20 << 8);
532 i2c.a_data_mask = 0x80;
533 i2c.en_clk_mask = (0x20 << 8);
534 i2c.en_data_mask = 0x80;
535 i2c.y_clk_mask = (0x20 << 8);
536 i2c.y_data_mask = 0x80;
537 } else {
538 /* default masks for ddc pads */
539 i2c.mask_clk_mask = RADEON_GPIO_MASK_1;
540 i2c.mask_data_mask = RADEON_GPIO_MASK_0;
541 i2c.a_clk_mask = RADEON_GPIO_A_1;
542 i2c.a_data_mask = RADEON_GPIO_A_0;
543 i2c.en_clk_mask = RADEON_GPIO_EN_1;
544 i2c.en_data_mask = RADEON_GPIO_EN_0;
545 i2c.y_clk_mask = RADEON_GPIO_Y_1;
546 i2c.y_data_mask = RADEON_GPIO_Y_0;
547 }
548
549 switch (rdev->family) {
550 case CHIP_R100:
551 case CHIP_RV100:
552 case CHIP_RS100:
553 case CHIP_RV200:
554 case CHIP_RS200:
555 case CHIP_RS300:
556 switch (ddc_line) {
557 case RADEON_GPIO_DVI_DDC:
558 i2c.hw_capable = true;
559 break;
560 default:
561 i2c.hw_capable = false;
562 break;
563 }
564 break;
565 case CHIP_R200:
566 switch (ddc_line) {
567 case RADEON_GPIO_DVI_DDC:
568 case RADEON_GPIO_MONID:
569 i2c.hw_capable = true;
570 break;
571 default:
572 i2c.hw_capable = false;
573 break;
574 }
575 break;
576 case CHIP_RV250:
577 case CHIP_RV280:
578 switch (ddc_line) {
579 case RADEON_GPIO_VGA_DDC:
580 case RADEON_GPIO_DVI_DDC:
581 case RADEON_GPIO_CRT2_DDC:
582 i2c.hw_capable = true;
583 break;
584 default:
585 i2c.hw_capable = false;
586 break;
587 }
588 break;
589 case CHIP_R300:
590 case CHIP_R350:
591 switch (ddc_line) {
592 case RADEON_GPIO_VGA_DDC:
593 case RADEON_GPIO_DVI_DDC:
594 i2c.hw_capable = true;
595 break;
596 default:
597 i2c.hw_capable = false;
598 break;
599 }
600 break;
601 case CHIP_RV350:
602 case CHIP_RV380:
603 case CHIP_RS400:
604 case CHIP_RS480:
605 switch (ddc_line) {
606 case RADEON_GPIO_VGA_DDC:
607 case RADEON_GPIO_DVI_DDC:
608 i2c.hw_capable = true;
609 break;
610 case RADEON_GPIO_MONID:
611 /* hw i2c on RADEON_GPIO_MONID doesn't seem to work
612 * reliably on some pre-r4xx hardware; not sure why.
613 */
614 i2c.hw_capable = false;
615 break;
616 default:
617 i2c.hw_capable = false;
618 break;
619 }
620 break;
621 default:
622 i2c.hw_capable = false;
623 break;
624 }
625 i2c.mm_i2c = false;
626
627 i2c.i2c_id = ddc;
628 i2c.hpd = RADEON_HPD_NONE;
629
630 if (ddc_line)
631 i2c.valid = true;
632 else
633 i2c.valid = false;
634
635 return i2c;
636 }
637
radeon_combios_get_i2c_info_from_table(struct radeon_device * rdev)638 static struct radeon_i2c_bus_rec radeon_combios_get_i2c_info_from_table(struct radeon_device *rdev)
639 {
640 struct drm_device *dev = rdev->ddev;
641 struct radeon_i2c_bus_rec i2c;
642 u16 offset;
643 u8 id, blocks, clk, data;
644 int i;
645
646 i2c.valid = false;
647
648 offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE);
649 if (offset) {
650 blocks = RBIOS8(offset + 2);
651 for (i = 0; i < blocks; i++) {
652 id = RBIOS8(offset + 3 + (i * 5) + 0);
653 if (id == 136) {
654 clk = RBIOS8(offset + 3 + (i * 5) + 3);
655 data = RBIOS8(offset + 3 + (i * 5) + 4);
656 /* gpiopad */
657 i2c = combios_setup_i2c_bus(rdev, DDC_MONID,
658 (1 << clk), (1 << data));
659 break;
660 }
661 }
662 }
663 return i2c;
664 }
665
radeon_combios_i2c_init(struct radeon_device * rdev)666 void radeon_combios_i2c_init(struct radeon_device *rdev)
667 {
668 struct drm_device *dev = rdev->ddev;
669 struct radeon_i2c_bus_rec i2c;
670
671 /* actual hw pads
672 * r1xx/rs2xx/rs3xx
673 * 0x60, 0x64, 0x68, 0x6c, gpiopads, mm
674 * r200
675 * 0x60, 0x64, 0x68, mm
676 * r300/r350
677 * 0x60, 0x64, mm
678 * rv2xx/rv3xx/rs4xx
679 * 0x60, 0x64, 0x68, gpiopads, mm
680 */
681
682 /* 0x60 */
683 i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
684 rdev->i2c_bus[0] = radeon_i2c_create(dev, &i2c, "DVI_DDC");
685 /* 0x64 */
686 i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
687 rdev->i2c_bus[1] = radeon_i2c_create(dev, &i2c, "VGA_DDC");
688
689 /* mm i2c */
690 i2c.valid = true;
691 i2c.hw_capable = true;
692 i2c.mm_i2c = true;
693 i2c.i2c_id = 0xa0;
694 rdev->i2c_bus[2] = radeon_i2c_create(dev, &i2c, "MM_I2C");
695
696 if (rdev->family == CHIP_R300 ||
697 rdev->family == CHIP_R350) {
698 /* only 2 sw i2c pads */
699 } else if (rdev->family == CHIP_RS300 ||
700 rdev->family == CHIP_RS400 ||
701 rdev->family == CHIP_RS480) {
702 /* 0x68 */
703 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
704 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
705
706 /* gpiopad */
707 i2c = radeon_combios_get_i2c_info_from_table(rdev);
708 if (i2c.valid)
709 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "GPIOPAD_MASK");
710 } else if ((rdev->family == CHIP_R200) ||
711 (rdev->family >= CHIP_R300)) {
712 /* 0x68 */
713 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
714 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
715 } else {
716 /* 0x68 */
717 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
718 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
719 /* 0x6c */
720 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
721 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "CRT2_DDC");
722 }
723 }
724
radeon_combios_get_clock_info(struct drm_device * dev)725 bool radeon_combios_get_clock_info(struct drm_device *dev)
726 {
727 struct radeon_device *rdev = dev->dev_private;
728 uint16_t pll_info;
729 struct radeon_pll *p1pll = &rdev->clock.p1pll;
730 struct radeon_pll *p2pll = &rdev->clock.p2pll;
731 struct radeon_pll *spll = &rdev->clock.spll;
732 struct radeon_pll *mpll = &rdev->clock.mpll;
733 int8_t rev;
734 uint16_t sclk, mclk;
735
736 pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE);
737 if (pll_info) {
738 rev = RBIOS8(pll_info);
739
740 /* pixel clocks */
741 p1pll->reference_freq = RBIOS16(pll_info + 0xe);
742 p1pll->reference_div = RBIOS16(pll_info + 0x10);
743 p1pll->pll_out_min = RBIOS32(pll_info + 0x12);
744 p1pll->pll_out_max = RBIOS32(pll_info + 0x16);
745 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
746 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
747
748 if (rev > 9) {
749 p1pll->pll_in_min = RBIOS32(pll_info + 0x36);
750 p1pll->pll_in_max = RBIOS32(pll_info + 0x3a);
751 } else {
752 p1pll->pll_in_min = 40;
753 p1pll->pll_in_max = 500;
754 }
755 *p2pll = *p1pll;
756
757 /* system clock */
758 spll->reference_freq = RBIOS16(pll_info + 0x1a);
759 spll->reference_div = RBIOS16(pll_info + 0x1c);
760 spll->pll_out_min = RBIOS32(pll_info + 0x1e);
761 spll->pll_out_max = RBIOS32(pll_info + 0x22);
762
763 if (rev > 10) {
764 spll->pll_in_min = RBIOS32(pll_info + 0x48);
765 spll->pll_in_max = RBIOS32(pll_info + 0x4c);
766 } else {
767 /* ??? */
768 spll->pll_in_min = 40;
769 spll->pll_in_max = 500;
770 }
771
772 /* memory clock */
773 mpll->reference_freq = RBIOS16(pll_info + 0x26);
774 mpll->reference_div = RBIOS16(pll_info + 0x28);
775 mpll->pll_out_min = RBIOS32(pll_info + 0x2a);
776 mpll->pll_out_max = RBIOS32(pll_info + 0x2e);
777
778 if (rev > 10) {
779 mpll->pll_in_min = RBIOS32(pll_info + 0x5a);
780 mpll->pll_in_max = RBIOS32(pll_info + 0x5e);
781 } else {
782 /* ??? */
783 mpll->pll_in_min = 40;
784 mpll->pll_in_max = 500;
785 }
786
787 /* default sclk/mclk */
788 sclk = RBIOS16(pll_info + 0xa);
789 mclk = RBIOS16(pll_info + 0x8);
790 if (sclk == 0)
791 sclk = 200 * 100;
792 if (mclk == 0)
793 mclk = 200 * 100;
794
795 rdev->clock.default_sclk = sclk;
796 rdev->clock.default_mclk = mclk;
797
798 if (RBIOS32(pll_info + 0x16))
799 rdev->clock.max_pixel_clock = RBIOS32(pll_info + 0x16);
800 else
801 rdev->clock.max_pixel_clock = 35000; /* might need something asic specific */
802
803 return true;
804 }
805 return false;
806 }
807
radeon_combios_sideport_present(struct radeon_device * rdev)808 bool radeon_combios_sideport_present(struct radeon_device *rdev)
809 {
810 struct drm_device *dev = rdev->ddev;
811 u16 igp_info;
812
813 /* sideport is AMD only */
814 if (rdev->family == CHIP_RS400)
815 return false;
816
817 igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE);
818
819 if (igp_info) {
820 if (RBIOS16(igp_info + 0x4))
821 return true;
822 }
823 return false;
824 }
825
826 static const uint32_t default_primarydac_adj[CHIP_LAST] = {
827 0x00000808, /* r100 */
828 0x00000808, /* rv100 */
829 0x00000808, /* rs100 */
830 0x00000808, /* rv200 */
831 0x00000808, /* rs200 */
832 0x00000808, /* r200 */
833 0x00000808, /* rv250 */
834 0x00000000, /* rs300 */
835 0x00000808, /* rv280 */
836 0x00000808, /* r300 */
837 0x00000808, /* r350 */
838 0x00000808, /* rv350 */
839 0x00000808, /* rv380 */
840 0x00000808, /* r420 */
841 0x00000808, /* r423 */
842 0x00000808, /* rv410 */
843 0x00000000, /* rs400 */
844 0x00000000, /* rs480 */
845 };
846
radeon_legacy_get_primary_dac_info_from_table(struct radeon_device * rdev,struct radeon_encoder_primary_dac * p_dac)847 static void radeon_legacy_get_primary_dac_info_from_table(struct radeon_device *rdev,
848 struct radeon_encoder_primary_dac *p_dac)
849 {
850 p_dac->ps2_pdac_adj = default_primarydac_adj[rdev->family];
851 return;
852 }
853
radeon_combios_get_primary_dac_info(struct radeon_encoder * encoder)854 struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
855 radeon_encoder
856 *encoder)
857 {
858 struct drm_device *dev = encoder->base.dev;
859 struct radeon_device *rdev = dev->dev_private;
860 uint16_t dac_info;
861 uint8_t rev, bg, dac;
862 struct radeon_encoder_primary_dac *p_dac = NULL;
863 int found = 0;
864
865 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac),
866 GFP_KERNEL);
867
868 if (!p_dac)
869 return NULL;
870
871 /* check CRT table */
872 dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
873 if (dac_info) {
874 rev = RBIOS8(dac_info) & 0x3;
875 if (rev < 2) {
876 bg = RBIOS8(dac_info + 0x2) & 0xf;
877 dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf;
878 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
879 } else {
880 bg = RBIOS8(dac_info + 0x2) & 0xf;
881 dac = RBIOS8(dac_info + 0x3) & 0xf;
882 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
883 }
884 /* if the values are zeros, use the table */
885 if ((dac == 0) || (bg == 0))
886 found = 0;
887 else
888 found = 1;
889 }
890
891 /* quirks */
892 /* Radeon 7000 (RV100) */
893 if (((dev->pdev->device == 0x5159) &&
894 (dev->pdev->subsystem_vendor == 0x174B) &&
895 (dev->pdev->subsystem_device == 0x7c28)) ||
896 /* Radeon 9100 (R200) */
897 ((dev->pdev->device == 0x514D) &&
898 (dev->pdev->subsystem_vendor == 0x174B) &&
899 (dev->pdev->subsystem_device == 0x7149))) {
900 /* vbios value is bad, use the default */
901 found = 0;
902 }
903
904 if (!found) /* fallback to defaults */
905 radeon_legacy_get_primary_dac_info_from_table(rdev, p_dac);
906
907 return p_dac;
908 }
909
910 enum radeon_tv_std
radeon_combios_get_tv_info(struct radeon_device * rdev)911 radeon_combios_get_tv_info(struct radeon_device *rdev)
912 {
913 struct drm_device *dev = rdev->ddev;
914 uint16_t tv_info;
915 enum radeon_tv_std tv_std = TV_STD_NTSC;
916
917 tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
918 if (tv_info) {
919 if (RBIOS8(tv_info + 6) == 'T') {
920 switch (RBIOS8(tv_info + 7) & 0xf) {
921 case 1:
922 tv_std = TV_STD_NTSC;
923 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
924 break;
925 case 2:
926 tv_std = TV_STD_PAL;
927 DRM_DEBUG_KMS("Default TV standard: PAL\n");
928 break;
929 case 3:
930 tv_std = TV_STD_PAL_M;
931 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
932 break;
933 case 4:
934 tv_std = TV_STD_PAL_60;
935 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
936 break;
937 case 5:
938 tv_std = TV_STD_NTSC_J;
939 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
940 break;
941 case 6:
942 tv_std = TV_STD_SCART_PAL;
943 DRM_DEBUG_KMS("Default TV standard: SCART-PAL\n");
944 break;
945 default:
946 tv_std = TV_STD_NTSC;
947 DRM_DEBUG_KMS
948 ("Unknown TV standard; defaulting to NTSC\n");
949 break;
950 }
951
952 switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) {
953 case 0:
954 DRM_DEBUG_KMS("29.498928713 MHz TV ref clk\n");
955 break;
956 case 1:
957 DRM_DEBUG_KMS("28.636360000 MHz TV ref clk\n");
958 break;
959 case 2:
960 DRM_DEBUG_KMS("14.318180000 MHz TV ref clk\n");
961 break;
962 case 3:
963 DRM_DEBUG_KMS("27.000000000 MHz TV ref clk\n");
964 break;
965 default:
966 break;
967 }
968 }
969 }
970 return tv_std;
971 }
972
973 static const uint32_t default_tvdac_adj[CHIP_LAST] = {
974 0x00000000, /* r100 */
975 0x00280000, /* rv100 */
976 0x00000000, /* rs100 */
977 0x00880000, /* rv200 */
978 0x00000000, /* rs200 */
979 0x00000000, /* r200 */
980 0x00770000, /* rv250 */
981 0x00290000, /* rs300 */
982 0x00560000, /* rv280 */
983 0x00780000, /* r300 */
984 0x00770000, /* r350 */
985 0x00780000, /* rv350 */
986 0x00780000, /* rv380 */
987 0x01080000, /* r420 */
988 0x01080000, /* r423 */
989 0x01080000, /* rv410 */
990 0x00780000, /* rs400 */
991 0x00780000, /* rs480 */
992 };
993
radeon_legacy_get_tv_dac_info_from_table(struct radeon_device * rdev,struct radeon_encoder_tv_dac * tv_dac)994 static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev,
995 struct radeon_encoder_tv_dac *tv_dac)
996 {
997 tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family];
998 if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250))
999 tv_dac->ps2_tvdac_adj = 0x00880000;
1000 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1001 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1002 return;
1003 }
1004
radeon_combios_get_tv_dac_info(struct radeon_encoder * encoder)1005 struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
1006 radeon_encoder
1007 *encoder)
1008 {
1009 struct drm_device *dev = encoder->base.dev;
1010 struct radeon_device *rdev = dev->dev_private;
1011 uint16_t dac_info;
1012 uint8_t rev, bg, dac;
1013 struct radeon_encoder_tv_dac *tv_dac = NULL;
1014 int found = 0;
1015
1016 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1017 if (!tv_dac)
1018 return NULL;
1019
1020 /* first check TV table */
1021 dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
1022 if (dac_info) {
1023 rev = RBIOS8(dac_info + 0x3);
1024 if (rev > 4) {
1025 bg = RBIOS8(dac_info + 0xc) & 0xf;
1026 dac = RBIOS8(dac_info + 0xd) & 0xf;
1027 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1028
1029 bg = RBIOS8(dac_info + 0xe) & 0xf;
1030 dac = RBIOS8(dac_info + 0xf) & 0xf;
1031 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1032
1033 bg = RBIOS8(dac_info + 0x10) & 0xf;
1034 dac = RBIOS8(dac_info + 0x11) & 0xf;
1035 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1036 /* if the values are all zeros, use the table */
1037 if (tv_dac->ps2_tvdac_adj)
1038 found = 1;
1039 } else if (rev > 1) {
1040 bg = RBIOS8(dac_info + 0xc) & 0xf;
1041 dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf;
1042 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1043
1044 bg = RBIOS8(dac_info + 0xd) & 0xf;
1045 dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf;
1046 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1047
1048 bg = RBIOS8(dac_info + 0xe) & 0xf;
1049 dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf;
1050 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1051 /* if the values are all zeros, use the table */
1052 if (tv_dac->ps2_tvdac_adj)
1053 found = 1;
1054 }
1055 tv_dac->tv_std = radeon_combios_get_tv_info(rdev);
1056 }
1057 if (!found) {
1058 /* then check CRT table */
1059 dac_info =
1060 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
1061 if (dac_info) {
1062 rev = RBIOS8(dac_info) & 0x3;
1063 if (rev < 2) {
1064 bg = RBIOS8(dac_info + 0x3) & 0xf;
1065 dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf;
1066 tv_dac->ps2_tvdac_adj =
1067 (bg << 16) | (dac << 20);
1068 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1069 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1070 /* if the values are all zeros, use the table */
1071 if (tv_dac->ps2_tvdac_adj)
1072 found = 1;
1073 } else {
1074 bg = RBIOS8(dac_info + 0x4) & 0xf;
1075 dac = RBIOS8(dac_info + 0x5) & 0xf;
1076 tv_dac->ps2_tvdac_adj =
1077 (bg << 16) | (dac << 20);
1078 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1079 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1080 /* if the values are all zeros, use the table */
1081 if (tv_dac->ps2_tvdac_adj)
1082 found = 1;
1083 }
1084 } else {
1085 DRM_INFO("No TV DAC info found in BIOS\n");
1086 }
1087 }
1088
1089 if (!found) /* fallback to defaults */
1090 radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac);
1091
1092 return tv_dac;
1093 }
1094
radeon_legacy_get_lvds_info_from_regs(struct radeon_device * rdev)1095 static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct
1096 radeon_device
1097 *rdev)
1098 {
1099 struct radeon_encoder_lvds *lvds = NULL;
1100 uint32_t fp_vert_stretch, fp_horz_stretch;
1101 uint32_t ppll_div_sel, ppll_val;
1102 uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
1103
1104 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1105
1106 if (!lvds)
1107 return NULL;
1108
1109 fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH);
1110 fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH);
1111
1112 /* These should be fail-safe defaults, fingers crossed */
1113 lvds->panel_pwr_delay = 200;
1114 lvds->panel_vcc_delay = 2000;
1115
1116 lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
1117 lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf;
1118 lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf;
1119
1120 if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE)
1121 lvds->native_mode.vdisplay =
1122 ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >>
1123 RADEON_VERT_PANEL_SHIFT) + 1;
1124 else
1125 lvds->native_mode.vdisplay =
1126 (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1;
1127
1128 if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE)
1129 lvds->native_mode.hdisplay =
1130 (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >>
1131 RADEON_HORZ_PANEL_SHIFT) + 1) * 8;
1132 else
1133 lvds->native_mode.hdisplay =
1134 ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8;
1135
1136 if ((lvds->native_mode.hdisplay < 640) ||
1137 (lvds->native_mode.vdisplay < 480)) {
1138 lvds->native_mode.hdisplay = 640;
1139 lvds->native_mode.vdisplay = 480;
1140 }
1141
1142 ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3;
1143 ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel);
1144 if ((ppll_val & 0x000707ff) == 0x1bb)
1145 lvds->use_bios_dividers = false;
1146 else {
1147 lvds->panel_ref_divider =
1148 RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
1149 lvds->panel_post_divider = (ppll_val >> 16) & 0x7;
1150 lvds->panel_fb_divider = ppll_val & 0x7ff;
1151
1152 if ((lvds->panel_ref_divider != 0) &&
1153 (lvds->panel_fb_divider > 3))
1154 lvds->use_bios_dividers = true;
1155 }
1156 lvds->panel_vcc_delay = 200;
1157
1158 DRM_INFO("Panel info derived from registers\n");
1159 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1160 lvds->native_mode.vdisplay);
1161
1162 return lvds;
1163 }
1164
radeon_combios_get_lvds_info(struct radeon_encoder * encoder)1165 struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
1166 *encoder)
1167 {
1168 struct drm_device *dev = encoder->base.dev;
1169 struct radeon_device *rdev = dev->dev_private;
1170 uint16_t lcd_info;
1171 uint32_t panel_setup;
1172 char stmp[30];
1173 int tmp, i;
1174 struct radeon_encoder_lvds *lvds = NULL;
1175
1176 lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
1177
1178 if (lcd_info) {
1179 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1180
1181 if (!lvds)
1182 return NULL;
1183
1184 for (i = 0; i < 24; i++)
1185 stmp[i] = RBIOS8(lcd_info + i + 1);
1186 stmp[24] = 0;
1187
1188 DRM_INFO("Panel ID String: %s\n", stmp);
1189
1190 lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19);
1191 lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b);
1192
1193 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1194 lvds->native_mode.vdisplay);
1195
1196 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c);
1197 lvds->panel_vcc_delay = min_t(u16, lvds->panel_vcc_delay, 2000);
1198
1199 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24);
1200 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf;
1201 lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf;
1202
1203 lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e);
1204 lvds->panel_post_divider = RBIOS8(lcd_info + 0x30);
1205 lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31);
1206 if ((lvds->panel_ref_divider != 0) &&
1207 (lvds->panel_fb_divider > 3))
1208 lvds->use_bios_dividers = true;
1209
1210 panel_setup = RBIOS32(lcd_info + 0x39);
1211 lvds->lvds_gen_cntl = 0xff00;
1212 if (panel_setup & 0x1)
1213 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT;
1214
1215 if ((panel_setup >> 4) & 0x1)
1216 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE;
1217
1218 switch ((panel_setup >> 8) & 0x7) {
1219 case 0:
1220 lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM;
1221 break;
1222 case 1:
1223 lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY;
1224 break;
1225 case 2:
1226 lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY;
1227 break;
1228 default:
1229 break;
1230 }
1231
1232 if ((panel_setup >> 16) & 0x1)
1233 lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW;
1234
1235 if ((panel_setup >> 17) & 0x1)
1236 lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW;
1237
1238 if ((panel_setup >> 18) & 0x1)
1239 lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW;
1240
1241 if ((panel_setup >> 23) & 0x1)
1242 lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL;
1243
1244 lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000);
1245
1246 for (i = 0; i < 32; i++) {
1247 tmp = RBIOS16(lcd_info + 64 + i * 2);
1248 if (tmp == 0)
1249 break;
1250
1251 if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) &&
1252 (RBIOS16(tmp + 2) == lvds->native_mode.vdisplay)) {
1253 u32 hss = (RBIOS16(tmp + 21) - RBIOS16(tmp + 19) - 1) * 8;
1254
1255 if (hss > lvds->native_mode.hdisplay)
1256 hss = (10 - 1) * 8;
1257
1258 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1259 (RBIOS16(tmp + 17) - RBIOS16(tmp + 19)) * 8;
1260 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1261 hss;
1262 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1263 (RBIOS8(tmp + 23) * 8);
1264
1265 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1266 (RBIOS16(tmp + 24) - RBIOS16(tmp + 26));
1267 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1268 ((RBIOS16(tmp + 28) & 0x7ff) - RBIOS16(tmp + 26));
1269 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1270 ((RBIOS16(tmp + 28) & 0xf800) >> 11);
1271
1272 lvds->native_mode.clock = RBIOS16(tmp + 9) * 10;
1273 lvds->native_mode.flags = 0;
1274 /* set crtc values */
1275 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1276
1277 }
1278 }
1279 } else {
1280 DRM_INFO("No panel info found in BIOS\n");
1281 lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
1282 }
1283
1284 if (lvds)
1285 encoder->native_mode = lvds->native_mode;
1286 return lvds;
1287 }
1288
1289 static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = {
1290 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R100 */
1291 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV100 */
1292 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS100 */
1293 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV200 */
1294 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RS200 */
1295 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R200 */
1296 {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}}, /* CHIP_RV250 */
1297 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS300 */
1298 {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}}, /* CHIP_RV280 */
1299 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R300 */
1300 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R350 */
1301 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV350 */
1302 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV380 */
1303 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R420 */
1304 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R423 */
1305 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RV410 */
1306 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS400 */
1307 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS480 */
1308 };
1309
radeon_legacy_get_tmds_info_from_table(struct radeon_encoder * encoder,struct radeon_encoder_int_tmds * tmds)1310 bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
1311 struct radeon_encoder_int_tmds *tmds)
1312 {
1313 struct drm_device *dev = encoder->base.dev;
1314 struct radeon_device *rdev = dev->dev_private;
1315 int i;
1316
1317 for (i = 0; i < 4; i++) {
1318 tmds->tmds_pll[i].value =
1319 default_tmds_pll[rdev->family][i].value;
1320 tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq;
1321 }
1322
1323 return true;
1324 }
1325
radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder * encoder,struct radeon_encoder_int_tmds * tmds)1326 bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
1327 struct radeon_encoder_int_tmds *tmds)
1328 {
1329 struct drm_device *dev = encoder->base.dev;
1330 struct radeon_device *rdev = dev->dev_private;
1331 uint16_t tmds_info;
1332 int i, n;
1333 uint8_t ver;
1334
1335 tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
1336
1337 if (tmds_info) {
1338 ver = RBIOS8(tmds_info);
1339 DRM_DEBUG_KMS("DFP table revision: %d\n", ver);
1340 if (ver == 3) {
1341 n = RBIOS8(tmds_info + 5) + 1;
1342 if (n > 4)
1343 n = 4;
1344 for (i = 0; i < n; i++) {
1345 tmds->tmds_pll[i].value =
1346 RBIOS32(tmds_info + i * 10 + 0x08);
1347 tmds->tmds_pll[i].freq =
1348 RBIOS16(tmds_info + i * 10 + 0x10);
1349 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
1350 tmds->tmds_pll[i].freq,
1351 tmds->tmds_pll[i].value);
1352 }
1353 } else if (ver == 4) {
1354 int stride = 0;
1355 n = RBIOS8(tmds_info + 5) + 1;
1356 if (n > 4)
1357 n = 4;
1358 for (i = 0; i < n; i++) {
1359 tmds->tmds_pll[i].value =
1360 RBIOS32(tmds_info + stride + 0x08);
1361 tmds->tmds_pll[i].freq =
1362 RBIOS16(tmds_info + stride + 0x10);
1363 if (i == 0)
1364 stride += 10;
1365 else
1366 stride += 6;
1367 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
1368 tmds->tmds_pll[i].freq,
1369 tmds->tmds_pll[i].value);
1370 }
1371 }
1372 } else {
1373 DRM_INFO("No TMDS info found in BIOS\n");
1374 return false;
1375 }
1376 return true;
1377 }
1378
radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder * encoder,struct radeon_encoder_ext_tmds * tmds)1379 bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
1380 struct radeon_encoder_ext_tmds *tmds)
1381 {
1382 struct drm_device *dev = encoder->base.dev;
1383 struct radeon_device *rdev = dev->dev_private;
1384 struct radeon_i2c_bus_rec i2c_bus;
1385
1386 /* default for macs */
1387 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1388 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1389
1390 /* XXX some macs have duallink chips */
1391 switch (rdev->mode_info.connector_table) {
1392 case CT_POWERBOOK_EXTERNAL:
1393 case CT_MINI_EXTERNAL:
1394 default:
1395 tmds->dvo_chip = DVO_SIL164;
1396 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1397 break;
1398 }
1399
1400 return true;
1401 }
1402
radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder * encoder,struct radeon_encoder_ext_tmds * tmds)1403 bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
1404 struct radeon_encoder_ext_tmds *tmds)
1405 {
1406 struct drm_device *dev = encoder->base.dev;
1407 struct radeon_device *rdev = dev->dev_private;
1408 uint16_t offset;
1409 uint8_t ver;
1410 enum radeon_combios_ddc gpio;
1411 struct radeon_i2c_bus_rec i2c_bus;
1412
1413 tmds->i2c_bus = NULL;
1414 if (rdev->flags & RADEON_IS_IGP) {
1415 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1416 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1417 tmds->dvo_chip = DVO_SIL164;
1418 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1419 } else {
1420 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1421 if (offset) {
1422 ver = RBIOS8(offset);
1423 DRM_DEBUG_KMS("External TMDS Table revision: %d\n", ver);
1424 tmds->slave_addr = RBIOS8(offset + 4 + 2);
1425 tmds->slave_addr >>= 1; /* 7 bit addressing */
1426 gpio = RBIOS8(offset + 4 + 3);
1427 if (gpio == DDC_LCD) {
1428 /* MM i2c */
1429 i2c_bus.valid = true;
1430 i2c_bus.hw_capable = true;
1431 i2c_bus.mm_i2c = true;
1432 i2c_bus.i2c_id = 0xa0;
1433 } else
1434 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0);
1435 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1436 }
1437 }
1438
1439 if (!tmds->i2c_bus) {
1440 DRM_INFO("No valid Ext TMDS info found in BIOS\n");
1441 return false;
1442 }
1443
1444 return true;
1445 }
1446
radeon_get_legacy_connector_info_from_table(struct drm_device * dev)1447 bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1448 {
1449 struct radeon_device *rdev = dev->dev_private;
1450 struct radeon_i2c_bus_rec ddc_i2c;
1451 struct radeon_hpd hpd;
1452
1453 rdev->mode_info.connector_table = radeon_connector_table;
1454 if (rdev->mode_info.connector_table == CT_NONE) {
1455 #ifdef CONFIG_PPC_PMAC
1456 if (of_machine_is_compatible("PowerBook3,3")) {
1457 /* powerbook with VGA */
1458 rdev->mode_info.connector_table = CT_POWERBOOK_VGA;
1459 } else if (of_machine_is_compatible("PowerBook3,4") ||
1460 of_machine_is_compatible("PowerBook3,5")) {
1461 /* powerbook with internal tmds */
1462 rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL;
1463 } else if (of_machine_is_compatible("PowerBook5,1") ||
1464 of_machine_is_compatible("PowerBook5,2") ||
1465 of_machine_is_compatible("PowerBook5,3") ||
1466 of_machine_is_compatible("PowerBook5,4") ||
1467 of_machine_is_compatible("PowerBook5,5")) {
1468 /* powerbook with external single link tmds (sil164) */
1469 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1470 } else if (of_machine_is_compatible("PowerBook5,6")) {
1471 /* powerbook with external dual or single link tmds */
1472 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1473 } else if (of_machine_is_compatible("PowerBook5,7") ||
1474 of_machine_is_compatible("PowerBook5,8") ||
1475 of_machine_is_compatible("PowerBook5,9")) {
1476 /* PowerBook6,2 ? */
1477 /* powerbook with external dual link tmds (sil1178?) */
1478 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1479 } else if (of_machine_is_compatible("PowerBook4,1") ||
1480 of_machine_is_compatible("PowerBook4,2") ||
1481 of_machine_is_compatible("PowerBook4,3") ||
1482 of_machine_is_compatible("PowerBook6,3") ||
1483 of_machine_is_compatible("PowerBook6,5") ||
1484 of_machine_is_compatible("PowerBook6,7")) {
1485 /* ibook */
1486 rdev->mode_info.connector_table = CT_IBOOK;
1487 } else if (of_machine_is_compatible("PowerMac3,5")) {
1488 /* PowerMac G4 Silver radeon 7500 */
1489 rdev->mode_info.connector_table = CT_MAC_G4_SILVER;
1490 } else if (of_machine_is_compatible("PowerMac4,4")) {
1491 /* emac */
1492 rdev->mode_info.connector_table = CT_EMAC;
1493 } else if (of_machine_is_compatible("PowerMac10,1")) {
1494 /* mini with internal tmds */
1495 rdev->mode_info.connector_table = CT_MINI_INTERNAL;
1496 } else if (of_machine_is_compatible("PowerMac10,2")) {
1497 /* mini with external tmds */
1498 rdev->mode_info.connector_table = CT_MINI_EXTERNAL;
1499 } else if (of_machine_is_compatible("PowerMac12,1")) {
1500 /* PowerMac8,1 ? */
1501 /* imac g5 isight */
1502 rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT;
1503 } else if ((rdev->pdev->device == 0x4a48) &&
1504 (rdev->pdev->subsystem_vendor == 0x1002) &&
1505 (rdev->pdev->subsystem_device == 0x4a48)) {
1506 /* Mac X800 */
1507 rdev->mode_info.connector_table = CT_MAC_X800;
1508 } else if ((of_machine_is_compatible("PowerMac7,2") ||
1509 of_machine_is_compatible("PowerMac7,3")) &&
1510 (rdev->pdev->device == 0x4150) &&
1511 (rdev->pdev->subsystem_vendor == 0x1002) &&
1512 (rdev->pdev->subsystem_device == 0x4150)) {
1513 /* Mac G5 tower 9600 */
1514 rdev->mode_info.connector_table = CT_MAC_G5_9600;
1515 } else if ((rdev->pdev->device == 0x4c66) &&
1516 (rdev->pdev->subsystem_vendor == 0x1002) &&
1517 (rdev->pdev->subsystem_device == 0x4c66)) {
1518 /* SAM440ep RV250 embedded board */
1519 rdev->mode_info.connector_table = CT_SAM440EP;
1520 } else
1521 #endif /* CONFIG_PPC_PMAC */
1522 #ifdef CONFIG_PPC64
1523 if (ASIC_IS_RN50(rdev))
1524 rdev->mode_info.connector_table = CT_RN50_POWER;
1525 else
1526 #endif
1527 rdev->mode_info.connector_table = CT_GENERIC;
1528 }
1529
1530 switch (rdev->mode_info.connector_table) {
1531 case CT_GENERIC:
1532 DRM_INFO("Connector Table: %d (generic)\n",
1533 rdev->mode_info.connector_table);
1534 /* these are the most common settings */
1535 if (rdev->flags & RADEON_SINGLE_CRTC) {
1536 /* VGA - primary dac */
1537 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1538 hpd.hpd = RADEON_HPD_NONE;
1539 radeon_add_legacy_encoder(dev,
1540 radeon_get_encoder_enum(dev,
1541 ATOM_DEVICE_CRT1_SUPPORT,
1542 1),
1543 ATOM_DEVICE_CRT1_SUPPORT);
1544 radeon_add_legacy_connector(dev, 0,
1545 ATOM_DEVICE_CRT1_SUPPORT,
1546 DRM_MODE_CONNECTOR_VGA,
1547 &ddc_i2c,
1548 CONNECTOR_OBJECT_ID_VGA,
1549 &hpd);
1550 } else if (rdev->flags & RADEON_IS_MOBILITY) {
1551 /* LVDS */
1552 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0);
1553 hpd.hpd = RADEON_HPD_NONE;
1554 radeon_add_legacy_encoder(dev,
1555 radeon_get_encoder_enum(dev,
1556 ATOM_DEVICE_LCD1_SUPPORT,
1557 0),
1558 ATOM_DEVICE_LCD1_SUPPORT);
1559 radeon_add_legacy_connector(dev, 0,
1560 ATOM_DEVICE_LCD1_SUPPORT,
1561 DRM_MODE_CONNECTOR_LVDS,
1562 &ddc_i2c,
1563 CONNECTOR_OBJECT_ID_LVDS,
1564 &hpd);
1565
1566 /* VGA - primary dac */
1567 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1568 hpd.hpd = RADEON_HPD_NONE;
1569 radeon_add_legacy_encoder(dev,
1570 radeon_get_encoder_enum(dev,
1571 ATOM_DEVICE_CRT1_SUPPORT,
1572 1),
1573 ATOM_DEVICE_CRT1_SUPPORT);
1574 radeon_add_legacy_connector(dev, 1,
1575 ATOM_DEVICE_CRT1_SUPPORT,
1576 DRM_MODE_CONNECTOR_VGA,
1577 &ddc_i2c,
1578 CONNECTOR_OBJECT_ID_VGA,
1579 &hpd);
1580 } else {
1581 /* DVI-I - tv dac, int tmds */
1582 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1583 hpd.hpd = RADEON_HPD_1;
1584 radeon_add_legacy_encoder(dev,
1585 radeon_get_encoder_enum(dev,
1586 ATOM_DEVICE_DFP1_SUPPORT,
1587 0),
1588 ATOM_DEVICE_DFP1_SUPPORT);
1589 radeon_add_legacy_encoder(dev,
1590 radeon_get_encoder_enum(dev,
1591 ATOM_DEVICE_CRT2_SUPPORT,
1592 2),
1593 ATOM_DEVICE_CRT2_SUPPORT);
1594 radeon_add_legacy_connector(dev, 0,
1595 ATOM_DEVICE_DFP1_SUPPORT |
1596 ATOM_DEVICE_CRT2_SUPPORT,
1597 DRM_MODE_CONNECTOR_DVII,
1598 &ddc_i2c,
1599 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1600 &hpd);
1601
1602 /* VGA - primary dac */
1603 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1604 hpd.hpd = RADEON_HPD_NONE;
1605 radeon_add_legacy_encoder(dev,
1606 radeon_get_encoder_enum(dev,
1607 ATOM_DEVICE_CRT1_SUPPORT,
1608 1),
1609 ATOM_DEVICE_CRT1_SUPPORT);
1610 radeon_add_legacy_connector(dev, 1,
1611 ATOM_DEVICE_CRT1_SUPPORT,
1612 DRM_MODE_CONNECTOR_VGA,
1613 &ddc_i2c,
1614 CONNECTOR_OBJECT_ID_VGA,
1615 &hpd);
1616 }
1617
1618 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
1619 /* TV - tv dac */
1620 ddc_i2c.valid = false;
1621 hpd.hpd = RADEON_HPD_NONE;
1622 radeon_add_legacy_encoder(dev,
1623 radeon_get_encoder_enum(dev,
1624 ATOM_DEVICE_TV1_SUPPORT,
1625 2),
1626 ATOM_DEVICE_TV1_SUPPORT);
1627 radeon_add_legacy_connector(dev, 2,
1628 ATOM_DEVICE_TV1_SUPPORT,
1629 DRM_MODE_CONNECTOR_SVIDEO,
1630 &ddc_i2c,
1631 CONNECTOR_OBJECT_ID_SVIDEO,
1632 &hpd);
1633 }
1634 break;
1635 case CT_IBOOK:
1636 DRM_INFO("Connector Table: %d (ibook)\n",
1637 rdev->mode_info.connector_table);
1638 /* LVDS */
1639 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1640 hpd.hpd = RADEON_HPD_NONE;
1641 radeon_add_legacy_encoder(dev,
1642 radeon_get_encoder_enum(dev,
1643 ATOM_DEVICE_LCD1_SUPPORT,
1644 0),
1645 ATOM_DEVICE_LCD1_SUPPORT);
1646 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1647 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1648 CONNECTOR_OBJECT_ID_LVDS,
1649 &hpd);
1650 /* VGA - TV DAC */
1651 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1652 hpd.hpd = RADEON_HPD_NONE;
1653 radeon_add_legacy_encoder(dev,
1654 radeon_get_encoder_enum(dev,
1655 ATOM_DEVICE_CRT2_SUPPORT,
1656 2),
1657 ATOM_DEVICE_CRT2_SUPPORT);
1658 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1659 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1660 CONNECTOR_OBJECT_ID_VGA,
1661 &hpd);
1662 /* TV - TV DAC */
1663 ddc_i2c.valid = false;
1664 hpd.hpd = RADEON_HPD_NONE;
1665 radeon_add_legacy_encoder(dev,
1666 radeon_get_encoder_enum(dev,
1667 ATOM_DEVICE_TV1_SUPPORT,
1668 2),
1669 ATOM_DEVICE_TV1_SUPPORT);
1670 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1671 DRM_MODE_CONNECTOR_SVIDEO,
1672 &ddc_i2c,
1673 CONNECTOR_OBJECT_ID_SVIDEO,
1674 &hpd);
1675 break;
1676 case CT_POWERBOOK_EXTERNAL:
1677 DRM_INFO("Connector Table: %d (powerbook external tmds)\n",
1678 rdev->mode_info.connector_table);
1679 /* LVDS */
1680 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1681 hpd.hpd = RADEON_HPD_NONE;
1682 radeon_add_legacy_encoder(dev,
1683 radeon_get_encoder_enum(dev,
1684 ATOM_DEVICE_LCD1_SUPPORT,
1685 0),
1686 ATOM_DEVICE_LCD1_SUPPORT);
1687 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1688 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1689 CONNECTOR_OBJECT_ID_LVDS,
1690 &hpd);
1691 /* DVI-I - primary dac, ext tmds */
1692 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1693 hpd.hpd = RADEON_HPD_2; /* ??? */
1694 radeon_add_legacy_encoder(dev,
1695 radeon_get_encoder_enum(dev,
1696 ATOM_DEVICE_DFP2_SUPPORT,
1697 0),
1698 ATOM_DEVICE_DFP2_SUPPORT);
1699 radeon_add_legacy_encoder(dev,
1700 radeon_get_encoder_enum(dev,
1701 ATOM_DEVICE_CRT1_SUPPORT,
1702 1),
1703 ATOM_DEVICE_CRT1_SUPPORT);
1704 /* XXX some are SL */
1705 radeon_add_legacy_connector(dev, 1,
1706 ATOM_DEVICE_DFP2_SUPPORT |
1707 ATOM_DEVICE_CRT1_SUPPORT,
1708 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1709 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
1710 &hpd);
1711 /* TV - TV DAC */
1712 ddc_i2c.valid = false;
1713 hpd.hpd = RADEON_HPD_NONE;
1714 radeon_add_legacy_encoder(dev,
1715 radeon_get_encoder_enum(dev,
1716 ATOM_DEVICE_TV1_SUPPORT,
1717 2),
1718 ATOM_DEVICE_TV1_SUPPORT);
1719 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1720 DRM_MODE_CONNECTOR_SVIDEO,
1721 &ddc_i2c,
1722 CONNECTOR_OBJECT_ID_SVIDEO,
1723 &hpd);
1724 break;
1725 case CT_POWERBOOK_INTERNAL:
1726 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n",
1727 rdev->mode_info.connector_table);
1728 /* LVDS */
1729 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1730 hpd.hpd = RADEON_HPD_NONE;
1731 radeon_add_legacy_encoder(dev,
1732 radeon_get_encoder_enum(dev,
1733 ATOM_DEVICE_LCD1_SUPPORT,
1734 0),
1735 ATOM_DEVICE_LCD1_SUPPORT);
1736 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1737 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1738 CONNECTOR_OBJECT_ID_LVDS,
1739 &hpd);
1740 /* DVI-I - primary dac, int tmds */
1741 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1742 hpd.hpd = RADEON_HPD_1; /* ??? */
1743 radeon_add_legacy_encoder(dev,
1744 radeon_get_encoder_enum(dev,
1745 ATOM_DEVICE_DFP1_SUPPORT,
1746 0),
1747 ATOM_DEVICE_DFP1_SUPPORT);
1748 radeon_add_legacy_encoder(dev,
1749 radeon_get_encoder_enum(dev,
1750 ATOM_DEVICE_CRT1_SUPPORT,
1751 1),
1752 ATOM_DEVICE_CRT1_SUPPORT);
1753 radeon_add_legacy_connector(dev, 1,
1754 ATOM_DEVICE_DFP1_SUPPORT |
1755 ATOM_DEVICE_CRT1_SUPPORT,
1756 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1757 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1758 &hpd);
1759 /* TV - TV DAC */
1760 ddc_i2c.valid = false;
1761 hpd.hpd = RADEON_HPD_NONE;
1762 radeon_add_legacy_encoder(dev,
1763 radeon_get_encoder_enum(dev,
1764 ATOM_DEVICE_TV1_SUPPORT,
1765 2),
1766 ATOM_DEVICE_TV1_SUPPORT);
1767 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1768 DRM_MODE_CONNECTOR_SVIDEO,
1769 &ddc_i2c,
1770 CONNECTOR_OBJECT_ID_SVIDEO,
1771 &hpd);
1772 break;
1773 case CT_POWERBOOK_VGA:
1774 DRM_INFO("Connector Table: %d (powerbook vga)\n",
1775 rdev->mode_info.connector_table);
1776 /* LVDS */
1777 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1778 hpd.hpd = RADEON_HPD_NONE;
1779 radeon_add_legacy_encoder(dev,
1780 radeon_get_encoder_enum(dev,
1781 ATOM_DEVICE_LCD1_SUPPORT,
1782 0),
1783 ATOM_DEVICE_LCD1_SUPPORT);
1784 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1785 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1786 CONNECTOR_OBJECT_ID_LVDS,
1787 &hpd);
1788 /* VGA - primary dac */
1789 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1790 hpd.hpd = RADEON_HPD_NONE;
1791 radeon_add_legacy_encoder(dev,
1792 radeon_get_encoder_enum(dev,
1793 ATOM_DEVICE_CRT1_SUPPORT,
1794 1),
1795 ATOM_DEVICE_CRT1_SUPPORT);
1796 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
1797 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1798 CONNECTOR_OBJECT_ID_VGA,
1799 &hpd);
1800 /* TV - TV DAC */
1801 ddc_i2c.valid = false;
1802 hpd.hpd = RADEON_HPD_NONE;
1803 radeon_add_legacy_encoder(dev,
1804 radeon_get_encoder_enum(dev,
1805 ATOM_DEVICE_TV1_SUPPORT,
1806 2),
1807 ATOM_DEVICE_TV1_SUPPORT);
1808 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1809 DRM_MODE_CONNECTOR_SVIDEO,
1810 &ddc_i2c,
1811 CONNECTOR_OBJECT_ID_SVIDEO,
1812 &hpd);
1813 break;
1814 case CT_MINI_EXTERNAL:
1815 DRM_INFO("Connector Table: %d (mini external tmds)\n",
1816 rdev->mode_info.connector_table);
1817 /* DVI-I - tv dac, ext tmds */
1818 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1819 hpd.hpd = RADEON_HPD_2; /* ??? */
1820 radeon_add_legacy_encoder(dev,
1821 radeon_get_encoder_enum(dev,
1822 ATOM_DEVICE_DFP2_SUPPORT,
1823 0),
1824 ATOM_DEVICE_DFP2_SUPPORT);
1825 radeon_add_legacy_encoder(dev,
1826 radeon_get_encoder_enum(dev,
1827 ATOM_DEVICE_CRT2_SUPPORT,
1828 2),
1829 ATOM_DEVICE_CRT2_SUPPORT);
1830 /* XXX are any DL? */
1831 radeon_add_legacy_connector(dev, 0,
1832 ATOM_DEVICE_DFP2_SUPPORT |
1833 ATOM_DEVICE_CRT2_SUPPORT,
1834 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1835 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1836 &hpd);
1837 /* TV - TV DAC */
1838 ddc_i2c.valid = false;
1839 hpd.hpd = RADEON_HPD_NONE;
1840 radeon_add_legacy_encoder(dev,
1841 radeon_get_encoder_enum(dev,
1842 ATOM_DEVICE_TV1_SUPPORT,
1843 2),
1844 ATOM_DEVICE_TV1_SUPPORT);
1845 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1846 DRM_MODE_CONNECTOR_SVIDEO,
1847 &ddc_i2c,
1848 CONNECTOR_OBJECT_ID_SVIDEO,
1849 &hpd);
1850 break;
1851 case CT_MINI_INTERNAL:
1852 DRM_INFO("Connector Table: %d (mini internal tmds)\n",
1853 rdev->mode_info.connector_table);
1854 /* DVI-I - tv dac, int tmds */
1855 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1856 hpd.hpd = RADEON_HPD_1; /* ??? */
1857 radeon_add_legacy_encoder(dev,
1858 radeon_get_encoder_enum(dev,
1859 ATOM_DEVICE_DFP1_SUPPORT,
1860 0),
1861 ATOM_DEVICE_DFP1_SUPPORT);
1862 radeon_add_legacy_encoder(dev,
1863 radeon_get_encoder_enum(dev,
1864 ATOM_DEVICE_CRT2_SUPPORT,
1865 2),
1866 ATOM_DEVICE_CRT2_SUPPORT);
1867 radeon_add_legacy_connector(dev, 0,
1868 ATOM_DEVICE_DFP1_SUPPORT |
1869 ATOM_DEVICE_CRT2_SUPPORT,
1870 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1871 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1872 &hpd);
1873 /* TV - TV DAC */
1874 ddc_i2c.valid = false;
1875 hpd.hpd = RADEON_HPD_NONE;
1876 radeon_add_legacy_encoder(dev,
1877 radeon_get_encoder_enum(dev,
1878 ATOM_DEVICE_TV1_SUPPORT,
1879 2),
1880 ATOM_DEVICE_TV1_SUPPORT);
1881 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1882 DRM_MODE_CONNECTOR_SVIDEO,
1883 &ddc_i2c,
1884 CONNECTOR_OBJECT_ID_SVIDEO,
1885 &hpd);
1886 break;
1887 case CT_IMAC_G5_ISIGHT:
1888 DRM_INFO("Connector Table: %d (imac g5 isight)\n",
1889 rdev->mode_info.connector_table);
1890 /* DVI-D - int tmds */
1891 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1892 hpd.hpd = RADEON_HPD_1; /* ??? */
1893 radeon_add_legacy_encoder(dev,
1894 radeon_get_encoder_enum(dev,
1895 ATOM_DEVICE_DFP1_SUPPORT,
1896 0),
1897 ATOM_DEVICE_DFP1_SUPPORT);
1898 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT,
1899 DRM_MODE_CONNECTOR_DVID, &ddc_i2c,
1900 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
1901 &hpd);
1902 /* VGA - tv dac */
1903 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1904 hpd.hpd = RADEON_HPD_NONE;
1905 radeon_add_legacy_encoder(dev,
1906 radeon_get_encoder_enum(dev,
1907 ATOM_DEVICE_CRT2_SUPPORT,
1908 2),
1909 ATOM_DEVICE_CRT2_SUPPORT);
1910 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1911 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1912 CONNECTOR_OBJECT_ID_VGA,
1913 &hpd);
1914 /* TV - TV DAC */
1915 ddc_i2c.valid = false;
1916 hpd.hpd = RADEON_HPD_NONE;
1917 radeon_add_legacy_encoder(dev,
1918 radeon_get_encoder_enum(dev,
1919 ATOM_DEVICE_TV1_SUPPORT,
1920 2),
1921 ATOM_DEVICE_TV1_SUPPORT);
1922 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1923 DRM_MODE_CONNECTOR_SVIDEO,
1924 &ddc_i2c,
1925 CONNECTOR_OBJECT_ID_SVIDEO,
1926 &hpd);
1927 break;
1928 case CT_EMAC:
1929 DRM_INFO("Connector Table: %d (emac)\n",
1930 rdev->mode_info.connector_table);
1931 /* VGA - primary dac */
1932 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1933 hpd.hpd = RADEON_HPD_NONE;
1934 radeon_add_legacy_encoder(dev,
1935 radeon_get_encoder_enum(dev,
1936 ATOM_DEVICE_CRT1_SUPPORT,
1937 1),
1938 ATOM_DEVICE_CRT1_SUPPORT);
1939 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
1940 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1941 CONNECTOR_OBJECT_ID_VGA,
1942 &hpd);
1943 /* VGA - tv dac */
1944 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1945 hpd.hpd = RADEON_HPD_NONE;
1946 radeon_add_legacy_encoder(dev,
1947 radeon_get_encoder_enum(dev,
1948 ATOM_DEVICE_CRT2_SUPPORT,
1949 2),
1950 ATOM_DEVICE_CRT2_SUPPORT);
1951 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1952 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1953 CONNECTOR_OBJECT_ID_VGA,
1954 &hpd);
1955 /* TV - TV DAC */
1956 ddc_i2c.valid = false;
1957 hpd.hpd = RADEON_HPD_NONE;
1958 radeon_add_legacy_encoder(dev,
1959 radeon_get_encoder_enum(dev,
1960 ATOM_DEVICE_TV1_SUPPORT,
1961 2),
1962 ATOM_DEVICE_TV1_SUPPORT);
1963 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1964 DRM_MODE_CONNECTOR_SVIDEO,
1965 &ddc_i2c,
1966 CONNECTOR_OBJECT_ID_SVIDEO,
1967 &hpd);
1968 break;
1969 case CT_RN50_POWER:
1970 DRM_INFO("Connector Table: %d (rn50-power)\n",
1971 rdev->mode_info.connector_table);
1972 /* VGA - primary dac */
1973 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1974 hpd.hpd = RADEON_HPD_NONE;
1975 radeon_add_legacy_encoder(dev,
1976 radeon_get_encoder_enum(dev,
1977 ATOM_DEVICE_CRT1_SUPPORT,
1978 1),
1979 ATOM_DEVICE_CRT1_SUPPORT);
1980 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
1981 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1982 CONNECTOR_OBJECT_ID_VGA,
1983 &hpd);
1984 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1985 hpd.hpd = RADEON_HPD_NONE;
1986 radeon_add_legacy_encoder(dev,
1987 radeon_get_encoder_enum(dev,
1988 ATOM_DEVICE_CRT2_SUPPORT,
1989 2),
1990 ATOM_DEVICE_CRT2_SUPPORT);
1991 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1992 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1993 CONNECTOR_OBJECT_ID_VGA,
1994 &hpd);
1995 break;
1996 case CT_MAC_X800:
1997 DRM_INFO("Connector Table: %d (mac x800)\n",
1998 rdev->mode_info.connector_table);
1999 /* DVI - primary dac, internal tmds */
2000 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2001 hpd.hpd = RADEON_HPD_1; /* ??? */
2002 radeon_add_legacy_encoder(dev,
2003 radeon_get_encoder_enum(dev,
2004 ATOM_DEVICE_DFP1_SUPPORT,
2005 0),
2006 ATOM_DEVICE_DFP1_SUPPORT);
2007 radeon_add_legacy_encoder(dev,
2008 radeon_get_encoder_enum(dev,
2009 ATOM_DEVICE_CRT1_SUPPORT,
2010 1),
2011 ATOM_DEVICE_CRT1_SUPPORT);
2012 radeon_add_legacy_connector(dev, 0,
2013 ATOM_DEVICE_DFP1_SUPPORT |
2014 ATOM_DEVICE_CRT1_SUPPORT,
2015 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2016 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2017 &hpd);
2018 /* DVI - tv dac, dvo */
2019 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
2020 hpd.hpd = RADEON_HPD_2; /* ??? */
2021 radeon_add_legacy_encoder(dev,
2022 radeon_get_encoder_enum(dev,
2023 ATOM_DEVICE_DFP2_SUPPORT,
2024 0),
2025 ATOM_DEVICE_DFP2_SUPPORT);
2026 radeon_add_legacy_encoder(dev,
2027 radeon_get_encoder_enum(dev,
2028 ATOM_DEVICE_CRT2_SUPPORT,
2029 2),
2030 ATOM_DEVICE_CRT2_SUPPORT);
2031 radeon_add_legacy_connector(dev, 1,
2032 ATOM_DEVICE_DFP2_SUPPORT |
2033 ATOM_DEVICE_CRT2_SUPPORT,
2034 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2035 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
2036 &hpd);
2037 break;
2038 case CT_MAC_G5_9600:
2039 DRM_INFO("Connector Table: %d (mac g5 9600)\n",
2040 rdev->mode_info.connector_table);
2041 /* DVI - tv dac, dvo */
2042 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2043 hpd.hpd = RADEON_HPD_1; /* ??? */
2044 radeon_add_legacy_encoder(dev,
2045 radeon_get_encoder_enum(dev,
2046 ATOM_DEVICE_DFP2_SUPPORT,
2047 0),
2048 ATOM_DEVICE_DFP2_SUPPORT);
2049 radeon_add_legacy_encoder(dev,
2050 radeon_get_encoder_enum(dev,
2051 ATOM_DEVICE_CRT2_SUPPORT,
2052 2),
2053 ATOM_DEVICE_CRT2_SUPPORT);
2054 radeon_add_legacy_connector(dev, 0,
2055 ATOM_DEVICE_DFP2_SUPPORT |
2056 ATOM_DEVICE_CRT2_SUPPORT,
2057 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2058 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2059 &hpd);
2060 /* ADC - primary dac, internal tmds */
2061 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2062 hpd.hpd = RADEON_HPD_2; /* ??? */
2063 radeon_add_legacy_encoder(dev,
2064 radeon_get_encoder_enum(dev,
2065 ATOM_DEVICE_DFP1_SUPPORT,
2066 0),
2067 ATOM_DEVICE_DFP1_SUPPORT);
2068 radeon_add_legacy_encoder(dev,
2069 radeon_get_encoder_enum(dev,
2070 ATOM_DEVICE_CRT1_SUPPORT,
2071 1),
2072 ATOM_DEVICE_CRT1_SUPPORT);
2073 radeon_add_legacy_connector(dev, 1,
2074 ATOM_DEVICE_DFP1_SUPPORT |
2075 ATOM_DEVICE_CRT1_SUPPORT,
2076 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2077 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2078 &hpd);
2079 /* TV - TV DAC */
2080 ddc_i2c.valid = false;
2081 hpd.hpd = RADEON_HPD_NONE;
2082 radeon_add_legacy_encoder(dev,
2083 radeon_get_encoder_enum(dev,
2084 ATOM_DEVICE_TV1_SUPPORT,
2085 2),
2086 ATOM_DEVICE_TV1_SUPPORT);
2087 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
2088 DRM_MODE_CONNECTOR_SVIDEO,
2089 &ddc_i2c,
2090 CONNECTOR_OBJECT_ID_SVIDEO,
2091 &hpd);
2092 break;
2093 case CT_SAM440EP:
2094 DRM_INFO("Connector Table: %d (SAM440ep embedded board)\n",
2095 rdev->mode_info.connector_table);
2096 /* LVDS */
2097 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0);
2098 hpd.hpd = RADEON_HPD_NONE;
2099 radeon_add_legacy_encoder(dev,
2100 radeon_get_encoder_enum(dev,
2101 ATOM_DEVICE_LCD1_SUPPORT,
2102 0),
2103 ATOM_DEVICE_LCD1_SUPPORT);
2104 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
2105 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
2106 CONNECTOR_OBJECT_ID_LVDS,
2107 &hpd);
2108 /* DVI-I - secondary dac, int tmds */
2109 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2110 hpd.hpd = RADEON_HPD_1; /* ??? */
2111 radeon_add_legacy_encoder(dev,
2112 radeon_get_encoder_enum(dev,
2113 ATOM_DEVICE_DFP1_SUPPORT,
2114 0),
2115 ATOM_DEVICE_DFP1_SUPPORT);
2116 radeon_add_legacy_encoder(dev,
2117 radeon_get_encoder_enum(dev,
2118 ATOM_DEVICE_CRT2_SUPPORT,
2119 2),
2120 ATOM_DEVICE_CRT2_SUPPORT);
2121 radeon_add_legacy_connector(dev, 1,
2122 ATOM_DEVICE_DFP1_SUPPORT |
2123 ATOM_DEVICE_CRT2_SUPPORT,
2124 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2125 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2126 &hpd);
2127 /* VGA - primary dac */
2128 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2129 hpd.hpd = RADEON_HPD_NONE;
2130 radeon_add_legacy_encoder(dev,
2131 radeon_get_encoder_enum(dev,
2132 ATOM_DEVICE_CRT1_SUPPORT,
2133 1),
2134 ATOM_DEVICE_CRT1_SUPPORT);
2135 radeon_add_legacy_connector(dev, 2,
2136 ATOM_DEVICE_CRT1_SUPPORT,
2137 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
2138 CONNECTOR_OBJECT_ID_VGA,
2139 &hpd);
2140 /* TV - TV DAC */
2141 ddc_i2c.valid = false;
2142 hpd.hpd = RADEON_HPD_NONE;
2143 radeon_add_legacy_encoder(dev,
2144 radeon_get_encoder_enum(dev,
2145 ATOM_DEVICE_TV1_SUPPORT,
2146 2),
2147 ATOM_DEVICE_TV1_SUPPORT);
2148 radeon_add_legacy_connector(dev, 3, ATOM_DEVICE_TV1_SUPPORT,
2149 DRM_MODE_CONNECTOR_SVIDEO,
2150 &ddc_i2c,
2151 CONNECTOR_OBJECT_ID_SVIDEO,
2152 &hpd);
2153 break;
2154 case CT_MAC_G4_SILVER:
2155 DRM_INFO("Connector Table: %d (mac g4 silver)\n",
2156 rdev->mode_info.connector_table);
2157 /* DVI-I - tv dac, int tmds */
2158 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2159 hpd.hpd = RADEON_HPD_1; /* ??? */
2160 radeon_add_legacy_encoder(dev,
2161 radeon_get_encoder_enum(dev,
2162 ATOM_DEVICE_DFP1_SUPPORT,
2163 0),
2164 ATOM_DEVICE_DFP1_SUPPORT);
2165 radeon_add_legacy_encoder(dev,
2166 radeon_get_encoder_enum(dev,
2167 ATOM_DEVICE_CRT2_SUPPORT,
2168 2),
2169 ATOM_DEVICE_CRT2_SUPPORT);
2170 radeon_add_legacy_connector(dev, 0,
2171 ATOM_DEVICE_DFP1_SUPPORT |
2172 ATOM_DEVICE_CRT2_SUPPORT,
2173 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2174 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2175 &hpd);
2176 /* VGA - primary dac */
2177 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2178 hpd.hpd = RADEON_HPD_NONE;
2179 radeon_add_legacy_encoder(dev,
2180 radeon_get_encoder_enum(dev,
2181 ATOM_DEVICE_CRT1_SUPPORT,
2182 1),
2183 ATOM_DEVICE_CRT1_SUPPORT);
2184 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
2185 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
2186 CONNECTOR_OBJECT_ID_VGA,
2187 &hpd);
2188 /* TV - TV DAC */
2189 ddc_i2c.valid = false;
2190 hpd.hpd = RADEON_HPD_NONE;
2191 radeon_add_legacy_encoder(dev,
2192 radeon_get_encoder_enum(dev,
2193 ATOM_DEVICE_TV1_SUPPORT,
2194 2),
2195 ATOM_DEVICE_TV1_SUPPORT);
2196 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
2197 DRM_MODE_CONNECTOR_SVIDEO,
2198 &ddc_i2c,
2199 CONNECTOR_OBJECT_ID_SVIDEO,
2200 &hpd);
2201 break;
2202 default:
2203 DRM_INFO("Connector table: %d (invalid)\n",
2204 rdev->mode_info.connector_table);
2205 return false;
2206 }
2207
2208 radeon_link_encoder_connector(dev);
2209
2210 return true;
2211 }
2212
radeon_apply_legacy_quirks(struct drm_device * dev,int bios_index,enum radeon_combios_connector * legacy_connector,struct radeon_i2c_bus_rec * ddc_i2c,struct radeon_hpd * hpd)2213 static bool radeon_apply_legacy_quirks(struct drm_device *dev,
2214 int bios_index,
2215 enum radeon_combios_connector
2216 *legacy_connector,
2217 struct radeon_i2c_bus_rec *ddc_i2c,
2218 struct radeon_hpd *hpd)
2219 {
2220
2221 /* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
2222 one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
2223 if (dev->pdev->device == 0x515e &&
2224 dev->pdev->subsystem_vendor == 0x1014) {
2225 if (*legacy_connector == CONNECTOR_CRT_LEGACY &&
2226 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
2227 return false;
2228 }
2229
2230 /* X300 card with extra non-existent DVI port */
2231 if (dev->pdev->device == 0x5B60 &&
2232 dev->pdev->subsystem_vendor == 0x17af &&
2233 dev->pdev->subsystem_device == 0x201e && bios_index == 2) {
2234 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
2235 return false;
2236 }
2237
2238 return true;
2239 }
2240
radeon_apply_legacy_tv_quirks(struct drm_device * dev)2241 static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev)
2242 {
2243 /* Acer 5102 has non-existent TV port */
2244 if (dev->pdev->device == 0x5975 &&
2245 dev->pdev->subsystem_vendor == 0x1025 &&
2246 dev->pdev->subsystem_device == 0x009f)
2247 return false;
2248
2249 /* HP dc5750 has non-existent TV port */
2250 if (dev->pdev->device == 0x5974 &&
2251 dev->pdev->subsystem_vendor == 0x103c &&
2252 dev->pdev->subsystem_device == 0x280a)
2253 return false;
2254
2255 /* MSI S270 has non-existent TV port */
2256 if (dev->pdev->device == 0x5955 &&
2257 dev->pdev->subsystem_vendor == 0x1462 &&
2258 dev->pdev->subsystem_device == 0x0131)
2259 return false;
2260
2261 return true;
2262 }
2263
combios_check_dl_dvi(struct drm_device * dev,int is_dvi_d)2264 static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d)
2265 {
2266 struct radeon_device *rdev = dev->dev_private;
2267 uint32_t ext_tmds_info;
2268
2269 if (rdev->flags & RADEON_IS_IGP) {
2270 if (is_dvi_d)
2271 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
2272 else
2273 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2274 }
2275 ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2276 if (ext_tmds_info) {
2277 uint8_t rev = RBIOS8(ext_tmds_info);
2278 uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5);
2279 if (rev >= 3) {
2280 if (is_dvi_d)
2281 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
2282 else
2283 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
2284 } else {
2285 if (flags & 1) {
2286 if (is_dvi_d)
2287 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
2288 else
2289 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
2290 }
2291 }
2292 }
2293 if (is_dvi_d)
2294 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
2295 else
2296 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2297 }
2298
radeon_get_legacy_connector_info_from_bios(struct drm_device * dev)2299 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
2300 {
2301 struct radeon_device *rdev = dev->dev_private;
2302 uint32_t conn_info, entry, devices;
2303 uint16_t tmp, connector_object_id;
2304 enum radeon_combios_ddc ddc_type;
2305 enum radeon_combios_connector connector;
2306 int i = 0;
2307 struct radeon_i2c_bus_rec ddc_i2c;
2308 struct radeon_hpd hpd;
2309
2310 conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE);
2311 if (conn_info) {
2312 for (i = 0; i < 4; i++) {
2313 entry = conn_info + 2 + i * 2;
2314
2315 if (!RBIOS16(entry))
2316 break;
2317
2318 tmp = RBIOS16(entry);
2319
2320 connector = (tmp >> 12) & 0xf;
2321
2322 ddc_type = (tmp >> 8) & 0xf;
2323 if (ddc_type == 5)
2324 ddc_i2c = radeon_combios_get_i2c_info_from_table(rdev);
2325 else
2326 ddc_i2c = combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
2327
2328 switch (connector) {
2329 case CONNECTOR_PROPRIETARY_LEGACY:
2330 case CONNECTOR_DVI_I_LEGACY:
2331 case CONNECTOR_DVI_D_LEGACY:
2332 if ((tmp >> 4) & 0x1)
2333 hpd.hpd = RADEON_HPD_2;
2334 else
2335 hpd.hpd = RADEON_HPD_1;
2336 break;
2337 default:
2338 hpd.hpd = RADEON_HPD_NONE;
2339 break;
2340 }
2341
2342 if (!radeon_apply_legacy_quirks(dev, i, &connector,
2343 &ddc_i2c, &hpd))
2344 continue;
2345
2346 switch (connector) {
2347 case CONNECTOR_PROPRIETARY_LEGACY:
2348 if ((tmp >> 4) & 0x1)
2349 devices = ATOM_DEVICE_DFP2_SUPPORT;
2350 else
2351 devices = ATOM_DEVICE_DFP1_SUPPORT;
2352 radeon_add_legacy_encoder(dev,
2353 radeon_get_encoder_enum
2354 (dev, devices, 0),
2355 devices);
2356 radeon_add_legacy_connector(dev, i, devices,
2357 legacy_connector_convert
2358 [connector],
2359 &ddc_i2c,
2360 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
2361 &hpd);
2362 break;
2363 case CONNECTOR_CRT_LEGACY:
2364 if (tmp & 0x1) {
2365 devices = ATOM_DEVICE_CRT2_SUPPORT;
2366 radeon_add_legacy_encoder(dev,
2367 radeon_get_encoder_enum
2368 (dev,
2369 ATOM_DEVICE_CRT2_SUPPORT,
2370 2),
2371 ATOM_DEVICE_CRT2_SUPPORT);
2372 } else {
2373 devices = ATOM_DEVICE_CRT1_SUPPORT;
2374 radeon_add_legacy_encoder(dev,
2375 radeon_get_encoder_enum
2376 (dev,
2377 ATOM_DEVICE_CRT1_SUPPORT,
2378 1),
2379 ATOM_DEVICE_CRT1_SUPPORT);
2380 }
2381 radeon_add_legacy_connector(dev,
2382 i,
2383 devices,
2384 legacy_connector_convert
2385 [connector],
2386 &ddc_i2c,
2387 CONNECTOR_OBJECT_ID_VGA,
2388 &hpd);
2389 break;
2390 case CONNECTOR_DVI_I_LEGACY:
2391 devices = 0;
2392 if (tmp & 0x1) {
2393 devices |= ATOM_DEVICE_CRT2_SUPPORT;
2394 radeon_add_legacy_encoder(dev,
2395 radeon_get_encoder_enum
2396 (dev,
2397 ATOM_DEVICE_CRT2_SUPPORT,
2398 2),
2399 ATOM_DEVICE_CRT2_SUPPORT);
2400 } else {
2401 devices |= ATOM_DEVICE_CRT1_SUPPORT;
2402 radeon_add_legacy_encoder(dev,
2403 radeon_get_encoder_enum
2404 (dev,
2405 ATOM_DEVICE_CRT1_SUPPORT,
2406 1),
2407 ATOM_DEVICE_CRT1_SUPPORT);
2408 }
2409 /* RV100 board with external TDMS bit mis-set.
2410 * Actually uses internal TMDS, clear the bit.
2411 */
2412 if (dev->pdev->device == 0x5159 &&
2413 dev->pdev->subsystem_vendor == 0x1014 &&
2414 dev->pdev->subsystem_device == 0x029A) {
2415 tmp &= ~(1 << 4);
2416 }
2417 if ((tmp >> 4) & 0x1) {
2418 devices |= ATOM_DEVICE_DFP2_SUPPORT;
2419 radeon_add_legacy_encoder(dev,
2420 radeon_get_encoder_enum
2421 (dev,
2422 ATOM_DEVICE_DFP2_SUPPORT,
2423 0),
2424 ATOM_DEVICE_DFP2_SUPPORT);
2425 connector_object_id = combios_check_dl_dvi(dev, 0);
2426 } else {
2427 devices |= ATOM_DEVICE_DFP1_SUPPORT;
2428 radeon_add_legacy_encoder(dev,
2429 radeon_get_encoder_enum
2430 (dev,
2431 ATOM_DEVICE_DFP1_SUPPORT,
2432 0),
2433 ATOM_DEVICE_DFP1_SUPPORT);
2434 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2435 }
2436 radeon_add_legacy_connector(dev,
2437 i,
2438 devices,
2439 legacy_connector_convert
2440 [connector],
2441 &ddc_i2c,
2442 connector_object_id,
2443 &hpd);
2444 break;
2445 case CONNECTOR_DVI_D_LEGACY:
2446 if ((tmp >> 4) & 0x1) {
2447 devices = ATOM_DEVICE_DFP2_SUPPORT;
2448 connector_object_id = combios_check_dl_dvi(dev, 1);
2449 } else {
2450 devices = ATOM_DEVICE_DFP1_SUPPORT;
2451 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2452 }
2453 radeon_add_legacy_encoder(dev,
2454 radeon_get_encoder_enum
2455 (dev, devices, 0),
2456 devices);
2457 radeon_add_legacy_connector(dev, i, devices,
2458 legacy_connector_convert
2459 [connector],
2460 &ddc_i2c,
2461 connector_object_id,
2462 &hpd);
2463 break;
2464 case CONNECTOR_CTV_LEGACY:
2465 case CONNECTOR_STV_LEGACY:
2466 radeon_add_legacy_encoder(dev,
2467 radeon_get_encoder_enum
2468 (dev,
2469 ATOM_DEVICE_TV1_SUPPORT,
2470 2),
2471 ATOM_DEVICE_TV1_SUPPORT);
2472 radeon_add_legacy_connector(dev, i,
2473 ATOM_DEVICE_TV1_SUPPORT,
2474 legacy_connector_convert
2475 [connector],
2476 &ddc_i2c,
2477 CONNECTOR_OBJECT_ID_SVIDEO,
2478 &hpd);
2479 break;
2480 default:
2481 DRM_ERROR("Unknown connector type: %d\n",
2482 connector);
2483 continue;
2484 }
2485
2486 }
2487 } else {
2488 uint16_t tmds_info =
2489 combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
2490 if (tmds_info) {
2491 DRM_DEBUG_KMS("Found DFP table, assuming DVI connector\n");
2492
2493 radeon_add_legacy_encoder(dev,
2494 radeon_get_encoder_enum(dev,
2495 ATOM_DEVICE_CRT1_SUPPORT,
2496 1),
2497 ATOM_DEVICE_CRT1_SUPPORT);
2498 radeon_add_legacy_encoder(dev,
2499 radeon_get_encoder_enum(dev,
2500 ATOM_DEVICE_DFP1_SUPPORT,
2501 0),
2502 ATOM_DEVICE_DFP1_SUPPORT);
2503
2504 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2505 hpd.hpd = RADEON_HPD_1;
2506 radeon_add_legacy_connector(dev,
2507 0,
2508 ATOM_DEVICE_CRT1_SUPPORT |
2509 ATOM_DEVICE_DFP1_SUPPORT,
2510 DRM_MODE_CONNECTOR_DVII,
2511 &ddc_i2c,
2512 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2513 &hpd);
2514 } else {
2515 uint16_t crt_info =
2516 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
2517 DRM_DEBUG_KMS("Found CRT table, assuming VGA connector\n");
2518 if (crt_info) {
2519 radeon_add_legacy_encoder(dev,
2520 radeon_get_encoder_enum(dev,
2521 ATOM_DEVICE_CRT1_SUPPORT,
2522 1),
2523 ATOM_DEVICE_CRT1_SUPPORT);
2524 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2525 hpd.hpd = RADEON_HPD_NONE;
2526 radeon_add_legacy_connector(dev,
2527 0,
2528 ATOM_DEVICE_CRT1_SUPPORT,
2529 DRM_MODE_CONNECTOR_VGA,
2530 &ddc_i2c,
2531 CONNECTOR_OBJECT_ID_VGA,
2532 &hpd);
2533 } else {
2534 DRM_DEBUG_KMS("No connector info found\n");
2535 return false;
2536 }
2537 }
2538 }
2539
2540 if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) {
2541 uint16_t lcd_info =
2542 combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
2543 if (lcd_info) {
2544 uint16_t lcd_ddc_info =
2545 combios_get_table_offset(dev,
2546 COMBIOS_LCD_DDC_INFO_TABLE);
2547
2548 radeon_add_legacy_encoder(dev,
2549 radeon_get_encoder_enum(dev,
2550 ATOM_DEVICE_LCD1_SUPPORT,
2551 0),
2552 ATOM_DEVICE_LCD1_SUPPORT);
2553
2554 if (lcd_ddc_info) {
2555 ddc_type = RBIOS8(lcd_ddc_info + 2);
2556 switch (ddc_type) {
2557 case DDC_LCD:
2558 ddc_i2c =
2559 combios_setup_i2c_bus(rdev,
2560 DDC_LCD,
2561 RBIOS32(lcd_ddc_info + 3),
2562 RBIOS32(lcd_ddc_info + 7));
2563 radeon_i2c_add(rdev, &ddc_i2c, "LCD");
2564 break;
2565 case DDC_GPIO:
2566 ddc_i2c =
2567 combios_setup_i2c_bus(rdev,
2568 DDC_GPIO,
2569 RBIOS32(lcd_ddc_info + 3),
2570 RBIOS32(lcd_ddc_info + 7));
2571 radeon_i2c_add(rdev, &ddc_i2c, "LCD");
2572 break;
2573 default:
2574 ddc_i2c =
2575 combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
2576 break;
2577 }
2578 DRM_DEBUG_KMS("LCD DDC Info Table found!\n");
2579 } else
2580 ddc_i2c.valid = false;
2581
2582 hpd.hpd = RADEON_HPD_NONE;
2583 radeon_add_legacy_connector(dev,
2584 5,
2585 ATOM_DEVICE_LCD1_SUPPORT,
2586 DRM_MODE_CONNECTOR_LVDS,
2587 &ddc_i2c,
2588 CONNECTOR_OBJECT_ID_LVDS,
2589 &hpd);
2590 }
2591 }
2592
2593 /* check TV table */
2594 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
2595 uint32_t tv_info =
2596 combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
2597 if (tv_info) {
2598 if (RBIOS8(tv_info + 6) == 'T') {
2599 if (radeon_apply_legacy_tv_quirks(dev)) {
2600 hpd.hpd = RADEON_HPD_NONE;
2601 ddc_i2c.valid = false;
2602 radeon_add_legacy_encoder(dev,
2603 radeon_get_encoder_enum
2604 (dev,
2605 ATOM_DEVICE_TV1_SUPPORT,
2606 2),
2607 ATOM_DEVICE_TV1_SUPPORT);
2608 radeon_add_legacy_connector(dev, 6,
2609 ATOM_DEVICE_TV1_SUPPORT,
2610 DRM_MODE_CONNECTOR_SVIDEO,
2611 &ddc_i2c,
2612 CONNECTOR_OBJECT_ID_SVIDEO,
2613 &hpd);
2614 }
2615 }
2616 }
2617 }
2618
2619 radeon_link_encoder_connector(dev);
2620
2621 return true;
2622 }
2623
2624 static const char *thermal_controller_names[] = {
2625 "NONE",
2626 "lm63",
2627 "adm1032",
2628 };
2629
radeon_combios_get_power_modes(struct radeon_device * rdev)2630 void radeon_combios_get_power_modes(struct radeon_device *rdev)
2631 {
2632 struct drm_device *dev = rdev->ddev;
2633 u16 offset, misc, misc2 = 0;
2634 u8 rev, blocks, tmp;
2635 int state_index = 0;
2636 struct radeon_i2c_bus_rec i2c_bus;
2637
2638 rdev->pm.default_power_state_index = -1;
2639
2640 /* allocate 2 power states */
2641 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * 2, GFP_KERNEL);
2642 if (rdev->pm.power_state) {
2643 /* allocate 1 clock mode per state */
2644 rdev->pm.power_state[0].clock_info =
2645 kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
2646 rdev->pm.power_state[1].clock_info =
2647 kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
2648 if (!rdev->pm.power_state[0].clock_info ||
2649 !rdev->pm.power_state[1].clock_info)
2650 goto pm_failed;
2651 } else
2652 goto pm_failed;
2653
2654 /* check for a thermal chip */
2655 offset = combios_get_table_offset(dev, COMBIOS_OVERDRIVE_INFO_TABLE);
2656 if (offset) {
2657 u8 thermal_controller = 0, gpio = 0, i2c_addr = 0, clk_bit = 0, data_bit = 0;
2658
2659 rev = RBIOS8(offset);
2660
2661 if (rev == 0) {
2662 thermal_controller = RBIOS8(offset + 3);
2663 gpio = RBIOS8(offset + 4) & 0x3f;
2664 i2c_addr = RBIOS8(offset + 5);
2665 } else if (rev == 1) {
2666 thermal_controller = RBIOS8(offset + 4);
2667 gpio = RBIOS8(offset + 5) & 0x3f;
2668 i2c_addr = RBIOS8(offset + 6);
2669 } else if (rev == 2) {
2670 thermal_controller = RBIOS8(offset + 4);
2671 gpio = RBIOS8(offset + 5) & 0x3f;
2672 i2c_addr = RBIOS8(offset + 6);
2673 clk_bit = RBIOS8(offset + 0xa);
2674 data_bit = RBIOS8(offset + 0xb);
2675 }
2676 if ((thermal_controller > 0) && (thermal_controller < 3)) {
2677 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
2678 thermal_controller_names[thermal_controller],
2679 i2c_addr >> 1);
2680 if (gpio == DDC_LCD) {
2681 /* MM i2c */
2682 i2c_bus.valid = true;
2683 i2c_bus.hw_capable = true;
2684 i2c_bus.mm_i2c = true;
2685 i2c_bus.i2c_id = 0xa0;
2686 } else if (gpio == DDC_GPIO)
2687 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 1 << clk_bit, 1 << data_bit);
2688 else
2689 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0);
2690 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2691 if (rdev->pm.i2c_bus) {
2692 struct i2c_board_info info = { };
2693 const char *name = thermal_controller_names[thermal_controller];
2694 info.addr = i2c_addr >> 1;
2695 strlcpy(info.type, name, sizeof(info.type));
2696 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2697 }
2698 }
2699 } else {
2700 /* boards with a thermal chip, but no overdrive table */
2701
2702 /* Asus 9600xt has an f75375 on the monid bus */
2703 if ((dev->pdev->device == 0x4152) &&
2704 (dev->pdev->subsystem_vendor == 0x1043) &&
2705 (dev->pdev->subsystem_device == 0xc002)) {
2706 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
2707 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2708 if (rdev->pm.i2c_bus) {
2709 struct i2c_board_info info = { };
2710 const char *name = "f75375";
2711 info.addr = 0x28;
2712 strlcpy(info.type, name, sizeof(info.type));
2713 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2714 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
2715 name, info.addr);
2716 }
2717 }
2718 }
2719
2720 if (rdev->flags & RADEON_IS_MOBILITY) {
2721 offset = combios_get_table_offset(dev, COMBIOS_POWERPLAY_INFO_TABLE);
2722 if (offset) {
2723 rev = RBIOS8(offset);
2724 blocks = RBIOS8(offset + 0x2);
2725 /* power mode 0 tends to be the only valid one */
2726 rdev->pm.power_state[state_index].num_clock_modes = 1;
2727 rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2);
2728 rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6);
2729 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2730 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2731 goto default_mode;
2732 rdev->pm.power_state[state_index].type =
2733 POWER_STATE_TYPE_BATTERY;
2734 misc = RBIOS16(offset + 0x5 + 0x0);
2735 if (rev > 4)
2736 misc2 = RBIOS16(offset + 0x5 + 0xe);
2737 rdev->pm.power_state[state_index].misc = misc;
2738 rdev->pm.power_state[state_index].misc2 = misc2;
2739 if (misc & 0x4) {
2740 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_GPIO;
2741 if (misc & 0x8)
2742 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2743 true;
2744 else
2745 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2746 false;
2747 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = true;
2748 if (rev < 6) {
2749 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2750 RBIOS16(offset + 0x5 + 0xb) * 4;
2751 tmp = RBIOS8(offset + 0x5 + 0xd);
2752 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2753 } else {
2754 u8 entries = RBIOS8(offset + 0x5 + 0xb);
2755 u16 voltage_table_offset = RBIOS16(offset + 0x5 + 0xc);
2756 if (entries && voltage_table_offset) {
2757 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2758 RBIOS16(voltage_table_offset) * 4;
2759 tmp = RBIOS8(voltage_table_offset + 0x2);
2760 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2761 } else
2762 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = false;
2763 }
2764 switch ((misc2 & 0x700) >> 8) {
2765 case 0:
2766 default:
2767 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 0;
2768 break;
2769 case 1:
2770 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 33;
2771 break;
2772 case 2:
2773 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 66;
2774 break;
2775 case 3:
2776 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 99;
2777 break;
2778 case 4:
2779 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 132;
2780 break;
2781 }
2782 } else
2783 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2784 if (rev > 6)
2785 rdev->pm.power_state[state_index].pcie_lanes =
2786 RBIOS8(offset + 0x5 + 0x10);
2787 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2788 state_index++;
2789 } else {
2790 /* XXX figure out some good default low power mode for mobility cards w/out power tables */
2791 }
2792 } else {
2793 /* XXX figure out some good default low power mode for desktop cards */
2794 }
2795
2796 default_mode:
2797 /* add the default mode */
2798 rdev->pm.power_state[state_index].type =
2799 POWER_STATE_TYPE_DEFAULT;
2800 rdev->pm.power_state[state_index].num_clock_modes = 1;
2801 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2802 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2803 rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0];
2804 if ((state_index > 0) &&
2805 (rdev->pm.power_state[0].clock_info[0].voltage.type == VOLTAGE_GPIO))
2806 rdev->pm.power_state[state_index].clock_info[0].voltage =
2807 rdev->pm.power_state[0].clock_info[0].voltage;
2808 else
2809 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2810 rdev->pm.power_state[state_index].pcie_lanes = 16;
2811 rdev->pm.power_state[state_index].flags = 0;
2812 rdev->pm.default_power_state_index = state_index;
2813 rdev->pm.num_power_states = state_index + 1;
2814
2815 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2816 rdev->pm.current_clock_mode_index = 0;
2817 return;
2818
2819 pm_failed:
2820 rdev->pm.default_power_state_index = state_index;
2821 rdev->pm.num_power_states = 0;
2822
2823 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2824 rdev->pm.current_clock_mode_index = 0;
2825 }
2826
radeon_external_tmds_setup(struct drm_encoder * encoder)2827 void radeon_external_tmds_setup(struct drm_encoder *encoder)
2828 {
2829 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2830 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2831
2832 if (!tmds)
2833 return;
2834
2835 switch (tmds->dvo_chip) {
2836 case DVO_SIL164:
2837 /* sil 164 */
2838 radeon_i2c_put_byte(tmds->i2c_bus,
2839 tmds->slave_addr,
2840 0x08, 0x30);
2841 radeon_i2c_put_byte(tmds->i2c_bus,
2842 tmds->slave_addr,
2843 0x09, 0x00);
2844 radeon_i2c_put_byte(tmds->i2c_bus,
2845 tmds->slave_addr,
2846 0x0a, 0x90);
2847 radeon_i2c_put_byte(tmds->i2c_bus,
2848 tmds->slave_addr,
2849 0x0c, 0x89);
2850 radeon_i2c_put_byte(tmds->i2c_bus,
2851 tmds->slave_addr,
2852 0x08, 0x3b);
2853 break;
2854 case DVO_SIL1178:
2855 /* sil 1178 - untested */
2856 /*
2857 * 0x0f, 0x44
2858 * 0x0f, 0x4c
2859 * 0x0e, 0x01
2860 * 0x0a, 0x80
2861 * 0x09, 0x30
2862 * 0x0c, 0xc9
2863 * 0x0d, 0x70
2864 * 0x08, 0x32
2865 * 0x08, 0x33
2866 */
2867 break;
2868 default:
2869 break;
2870 }
2871
2872 }
2873
radeon_combios_external_tmds_setup(struct drm_encoder * encoder)2874 bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder)
2875 {
2876 struct drm_device *dev = encoder->dev;
2877 struct radeon_device *rdev = dev->dev_private;
2878 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2879 uint16_t offset;
2880 uint8_t blocks, slave_addr, rev;
2881 uint32_t index, id;
2882 uint32_t reg, val, and_mask, or_mask;
2883 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2884
2885 if (!tmds)
2886 return false;
2887
2888 if (rdev->flags & RADEON_IS_IGP) {
2889 offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_ON_TABLE);
2890 rev = RBIOS8(offset);
2891 if (offset) {
2892 rev = RBIOS8(offset);
2893 if (rev > 1) {
2894 blocks = RBIOS8(offset + 3);
2895 index = offset + 4;
2896 while (blocks > 0) {
2897 id = RBIOS16(index);
2898 index += 2;
2899 switch (id >> 13) {
2900 case 0:
2901 reg = (id & 0x1fff) * 4;
2902 val = RBIOS32(index);
2903 index += 4;
2904 WREG32(reg, val);
2905 break;
2906 case 2:
2907 reg = (id & 0x1fff) * 4;
2908 and_mask = RBIOS32(index);
2909 index += 4;
2910 or_mask = RBIOS32(index);
2911 index += 4;
2912 val = RREG32(reg);
2913 val = (val & and_mask) | or_mask;
2914 WREG32(reg, val);
2915 break;
2916 case 3:
2917 val = RBIOS16(index);
2918 index += 2;
2919 udelay(val);
2920 break;
2921 case 4:
2922 val = RBIOS16(index);
2923 index += 2;
2924 mdelay(val);
2925 break;
2926 case 6:
2927 slave_addr = id & 0xff;
2928 slave_addr >>= 1; /* 7 bit addressing */
2929 index++;
2930 reg = RBIOS8(index);
2931 index++;
2932 val = RBIOS8(index);
2933 index++;
2934 radeon_i2c_put_byte(tmds->i2c_bus,
2935 slave_addr,
2936 reg, val);
2937 break;
2938 default:
2939 DRM_ERROR("Unknown id %d\n", id >> 13);
2940 break;
2941 }
2942 blocks--;
2943 }
2944 return true;
2945 }
2946 }
2947 } else {
2948 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2949 if (offset) {
2950 index = offset + 10;
2951 id = RBIOS16(index);
2952 while (id != 0xffff) {
2953 index += 2;
2954 switch (id >> 13) {
2955 case 0:
2956 reg = (id & 0x1fff) * 4;
2957 val = RBIOS32(index);
2958 WREG32(reg, val);
2959 break;
2960 case 2:
2961 reg = (id & 0x1fff) * 4;
2962 and_mask = RBIOS32(index);
2963 index += 4;
2964 or_mask = RBIOS32(index);
2965 index += 4;
2966 val = RREG32(reg);
2967 val = (val & and_mask) | or_mask;
2968 WREG32(reg, val);
2969 break;
2970 case 4:
2971 val = RBIOS16(index);
2972 index += 2;
2973 udelay(val);
2974 break;
2975 case 5:
2976 reg = id & 0x1fff;
2977 and_mask = RBIOS32(index);
2978 index += 4;
2979 or_mask = RBIOS32(index);
2980 index += 4;
2981 val = RREG32_PLL(reg);
2982 val = (val & and_mask) | or_mask;
2983 WREG32_PLL(reg, val);
2984 break;
2985 case 6:
2986 reg = id & 0x1fff;
2987 val = RBIOS8(index);
2988 index += 1;
2989 radeon_i2c_put_byte(tmds->i2c_bus,
2990 tmds->slave_addr,
2991 reg, val);
2992 break;
2993 default:
2994 DRM_ERROR("Unknown id %d\n", id >> 13);
2995 break;
2996 }
2997 id = RBIOS16(index);
2998 }
2999 return true;
3000 }
3001 }
3002 return false;
3003 }
3004
combios_parse_mmio_table(struct drm_device * dev,uint16_t offset)3005 static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset)
3006 {
3007 struct radeon_device *rdev = dev->dev_private;
3008
3009 if (offset) {
3010 while (RBIOS16(offset)) {
3011 uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13);
3012 uint32_t addr = (RBIOS16(offset) & 0x1fff);
3013 uint32_t val, and_mask, or_mask;
3014 uint32_t tmp;
3015
3016 offset += 2;
3017 switch (cmd) {
3018 case 0:
3019 val = RBIOS32(offset);
3020 offset += 4;
3021 WREG32(addr, val);
3022 break;
3023 case 1:
3024 val = RBIOS32(offset);
3025 offset += 4;
3026 WREG32(addr, val);
3027 break;
3028 case 2:
3029 and_mask = RBIOS32(offset);
3030 offset += 4;
3031 or_mask = RBIOS32(offset);
3032 offset += 4;
3033 tmp = RREG32(addr);
3034 tmp &= and_mask;
3035 tmp |= or_mask;
3036 WREG32(addr, tmp);
3037 break;
3038 case 3:
3039 and_mask = RBIOS32(offset);
3040 offset += 4;
3041 or_mask = RBIOS32(offset);
3042 offset += 4;
3043 tmp = RREG32(addr);
3044 tmp &= and_mask;
3045 tmp |= or_mask;
3046 WREG32(addr, tmp);
3047 break;
3048 case 4:
3049 val = RBIOS16(offset);
3050 offset += 2;
3051 udelay(val);
3052 break;
3053 case 5:
3054 val = RBIOS16(offset);
3055 offset += 2;
3056 switch (addr) {
3057 case 8:
3058 while (val--) {
3059 if (!
3060 (RREG32_PLL
3061 (RADEON_CLK_PWRMGT_CNTL) &
3062 RADEON_MC_BUSY))
3063 break;
3064 }
3065 break;
3066 case 9:
3067 while (val--) {
3068 if ((RREG32(RADEON_MC_STATUS) &
3069 RADEON_MC_IDLE))
3070 break;
3071 }
3072 break;
3073 default:
3074 break;
3075 }
3076 break;
3077 default:
3078 break;
3079 }
3080 }
3081 }
3082 }
3083
combios_parse_pll_table(struct drm_device * dev,uint16_t offset)3084 static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)
3085 {
3086 struct radeon_device *rdev = dev->dev_private;
3087
3088 if (offset) {
3089 while (RBIOS8(offset)) {
3090 uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6);
3091 uint8_t addr = (RBIOS8(offset) & 0x3f);
3092 uint32_t val, shift, tmp;
3093 uint32_t and_mask, or_mask;
3094
3095 offset++;
3096 switch (cmd) {
3097 case 0:
3098 val = RBIOS32(offset);
3099 offset += 4;
3100 WREG32_PLL(addr, val);
3101 break;
3102 case 1:
3103 shift = RBIOS8(offset) * 8;
3104 offset++;
3105 and_mask = RBIOS8(offset) << shift;
3106 and_mask |= ~(0xff << shift);
3107 offset++;
3108 or_mask = RBIOS8(offset) << shift;
3109 offset++;
3110 tmp = RREG32_PLL(addr);
3111 tmp &= and_mask;
3112 tmp |= or_mask;
3113 WREG32_PLL(addr, tmp);
3114 break;
3115 case 2:
3116 case 3:
3117 tmp = 1000;
3118 switch (addr) {
3119 case 1:
3120 udelay(150);
3121 break;
3122 case 2:
3123 mdelay(1);
3124 break;
3125 case 3:
3126 while (tmp--) {
3127 if (!
3128 (RREG32_PLL
3129 (RADEON_CLK_PWRMGT_CNTL) &
3130 RADEON_MC_BUSY))
3131 break;
3132 }
3133 break;
3134 case 4:
3135 while (tmp--) {
3136 if (RREG32_PLL
3137 (RADEON_CLK_PWRMGT_CNTL) &
3138 RADEON_DLL_READY)
3139 break;
3140 }
3141 break;
3142 case 5:
3143 tmp =
3144 RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
3145 if (tmp & RADEON_CG_NO1_DEBUG_0) {
3146 #if 0
3147 uint32_t mclk_cntl =
3148 RREG32_PLL
3149 (RADEON_MCLK_CNTL);
3150 mclk_cntl &= 0xffff0000;
3151 /*mclk_cntl |= 0x00001111;*//* ??? */
3152 WREG32_PLL(RADEON_MCLK_CNTL,
3153 mclk_cntl);
3154 mdelay(10);
3155 #endif
3156 WREG32_PLL
3157 (RADEON_CLK_PWRMGT_CNTL,
3158 tmp &
3159 ~RADEON_CG_NO1_DEBUG_0);
3160 mdelay(10);
3161 }
3162 break;
3163 default:
3164 break;
3165 }
3166 break;
3167 default:
3168 break;
3169 }
3170 }
3171 }
3172 }
3173
combios_parse_ram_reset_table(struct drm_device * dev,uint16_t offset)3174 static void combios_parse_ram_reset_table(struct drm_device *dev,
3175 uint16_t offset)
3176 {
3177 struct radeon_device *rdev = dev->dev_private;
3178 uint32_t tmp;
3179
3180 if (offset) {
3181 uint8_t val = RBIOS8(offset);
3182 while (val != 0xff) {
3183 offset++;
3184
3185 if (val == 0x0f) {
3186 uint32_t channel_complete_mask;
3187
3188 if (ASIC_IS_R300(rdev))
3189 channel_complete_mask =
3190 R300_MEM_PWRUP_COMPLETE;
3191 else
3192 channel_complete_mask =
3193 RADEON_MEM_PWRUP_COMPLETE;
3194 tmp = 20000;
3195 while (tmp--) {
3196 if ((RREG32(RADEON_MEM_STR_CNTL) &
3197 channel_complete_mask) ==
3198 channel_complete_mask)
3199 break;
3200 }
3201 } else {
3202 uint32_t or_mask = RBIOS16(offset);
3203 offset += 2;
3204
3205 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3206 tmp &= RADEON_SDRAM_MODE_MASK;
3207 tmp |= or_mask;
3208 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
3209
3210 or_mask = val << 24;
3211 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3212 tmp &= RADEON_B3MEM_RESET_MASK;
3213 tmp |= or_mask;
3214 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
3215 }
3216 val = RBIOS8(offset);
3217 }
3218 }
3219 }
3220
combios_detect_ram(struct drm_device * dev,int ram,int mem_addr_mapping)3221 static uint32_t combios_detect_ram(struct drm_device *dev, int ram,
3222 int mem_addr_mapping)
3223 {
3224 struct radeon_device *rdev = dev->dev_private;
3225 uint32_t mem_cntl;
3226 uint32_t mem_size;
3227 uint32_t addr = 0;
3228
3229 mem_cntl = RREG32(RADEON_MEM_CNTL);
3230 if (mem_cntl & RV100_HALF_MODE)
3231 ram /= 2;
3232 mem_size = ram;
3233 mem_cntl &= ~(0xff << 8);
3234 mem_cntl |= (mem_addr_mapping & 0xff) << 8;
3235 WREG32(RADEON_MEM_CNTL, mem_cntl);
3236 RREG32(RADEON_MEM_CNTL);
3237
3238 /* sdram reset ? */
3239
3240 /* something like this???? */
3241 while (ram--) {
3242 addr = ram * 1024 * 1024;
3243 /* write to each page */
3244 WREG32_IDX((addr) | RADEON_MM_APER, 0xdeadbeef);
3245 /* read back and verify */
3246 if (RREG32_IDX((addr) | RADEON_MM_APER) != 0xdeadbeef)
3247 return 0;
3248 }
3249
3250 return mem_size;
3251 }
3252
combios_write_ram_size(struct drm_device * dev)3253 static void combios_write_ram_size(struct drm_device *dev)
3254 {
3255 struct radeon_device *rdev = dev->dev_private;
3256 uint8_t rev;
3257 uint16_t offset;
3258 uint32_t mem_size = 0;
3259 uint32_t mem_cntl = 0;
3260
3261 /* should do something smarter here I guess... */
3262 if (rdev->flags & RADEON_IS_IGP)
3263 return;
3264
3265 /* first check detected mem table */
3266 offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE);
3267 if (offset) {
3268 rev = RBIOS8(offset);
3269 if (rev < 3) {
3270 mem_cntl = RBIOS32(offset + 1);
3271 mem_size = RBIOS16(offset + 5);
3272 if ((rdev->family < CHIP_R200) &&
3273 !ASIC_IS_RN50(rdev))
3274 WREG32(RADEON_MEM_CNTL, mem_cntl);
3275 }
3276 }
3277
3278 if (!mem_size) {
3279 offset =
3280 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
3281 if (offset) {
3282 rev = RBIOS8(offset - 1);
3283 if (rev < 1) {
3284 if ((rdev->family < CHIP_R200)
3285 && !ASIC_IS_RN50(rdev)) {
3286 int ram = 0;
3287 int mem_addr_mapping = 0;
3288
3289 while (RBIOS8(offset)) {
3290 ram = RBIOS8(offset);
3291 mem_addr_mapping =
3292 RBIOS8(offset + 1);
3293 if (mem_addr_mapping != 0x25)
3294 ram *= 2;
3295 mem_size =
3296 combios_detect_ram(dev, ram,
3297 mem_addr_mapping);
3298 if (mem_size)
3299 break;
3300 offset += 2;
3301 }
3302 } else
3303 mem_size = RBIOS8(offset);
3304 } else {
3305 mem_size = RBIOS8(offset);
3306 mem_size *= 2; /* convert to MB */
3307 }
3308 }
3309 }
3310
3311 mem_size *= (1024 * 1024); /* convert to bytes */
3312 WREG32(RADEON_CONFIG_MEMSIZE, mem_size);
3313 }
3314
radeon_combios_asic_init(struct drm_device * dev)3315 void radeon_combios_asic_init(struct drm_device *dev)
3316 {
3317 struct radeon_device *rdev = dev->dev_private;
3318 uint16_t table;
3319
3320 /* port hardcoded mac stuff from radeonfb */
3321 if (rdev->bios == NULL)
3322 return;
3323
3324 /* ASIC INIT 1 */
3325 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE);
3326 if (table)
3327 combios_parse_mmio_table(dev, table);
3328
3329 /* PLL INIT */
3330 table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE);
3331 if (table)
3332 combios_parse_pll_table(dev, table);
3333
3334 /* ASIC INIT 2 */
3335 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE);
3336 if (table)
3337 combios_parse_mmio_table(dev, table);
3338
3339 if (!(rdev->flags & RADEON_IS_IGP)) {
3340 /* ASIC INIT 4 */
3341 table =
3342 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE);
3343 if (table)
3344 combios_parse_mmio_table(dev, table);
3345
3346 /* RAM RESET */
3347 table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE);
3348 if (table)
3349 combios_parse_ram_reset_table(dev, table);
3350
3351 /* ASIC INIT 3 */
3352 table =
3353 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE);
3354 if (table)
3355 combios_parse_mmio_table(dev, table);
3356
3357 /* write CONFIG_MEMSIZE */
3358 combios_write_ram_size(dev);
3359 }
3360
3361 /* quirk for rs4xx HP nx6125 laptop to make it resume
3362 * - it hangs on resume inside the dynclk 1 table.
3363 */
3364 if (rdev->family == CHIP_RS480 &&
3365 rdev->pdev->subsystem_vendor == 0x103c &&
3366 rdev->pdev->subsystem_device == 0x308b)
3367 return;
3368
3369 /* quirk for rs4xx HP dv5000 laptop to make it resume
3370 * - it hangs on resume inside the dynclk 1 table.
3371 */
3372 if (rdev->family == CHIP_RS480 &&
3373 rdev->pdev->subsystem_vendor == 0x103c &&
3374 rdev->pdev->subsystem_device == 0x30a4)
3375 return;
3376
3377 /* quirk for rs4xx Compaq Presario V5245EU laptop to make it resume
3378 * - it hangs on resume inside the dynclk 1 table.
3379 */
3380 if (rdev->family == CHIP_RS480 &&
3381 rdev->pdev->subsystem_vendor == 0x103c &&
3382 rdev->pdev->subsystem_device == 0x30ae)
3383 return;
3384 /* quirk for rs4xx Toshiba Sattellite L20-183 latop to make it resume
3385 * - it hangs on resume inside the dynclk 1 table.
3386 */
3387 if (rdev->family == CHIP_RS400 &&
3388 rdev->pdev->subsystem_vendor == 0x1179 &&
3389 rdev->pdev->subsystem_device == 0xff31)
3390 return;
3391
3392 /* quirk for rs4xx HP Compaq dc5750 Small Form Factor to make it resume
3393 * - it hangs on resume inside the dynclk 1 table.
3394 */
3395 if (rdev->family == CHIP_RS480 &&
3396 rdev->pdev->subsystem_vendor == 0x103c &&
3397 rdev->pdev->subsystem_device == 0x280a)
3398 return;
3399 /* quirk for rs4xx Toshiba Sattellite L20-183 latop to make it resume
3400 * - it hangs on resume inside the dynclk 1 table.
3401 */
3402 if (rdev->family == CHIP_RS400 &&
3403 rdev->pdev->subsystem_vendor == 0x1179 &&
3404 rdev->pdev->subsystem_device == 0xff31)
3405 return;
3406
3407 /* DYN CLK 1 */
3408 table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
3409 if (table)
3410 combios_parse_pll_table(dev, table);
3411
3412 }
3413
radeon_combios_initialize_bios_scratch_regs(struct drm_device * dev)3414 void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev)
3415 {
3416 struct radeon_device *rdev = dev->dev_private;
3417 uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch;
3418
3419 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
3420 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3421 bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH);
3422
3423 /* let the bios control the backlight */
3424 bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN;
3425
3426 /* tell the bios not to handle mode switching */
3427 bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS |
3428 RADEON_ACC_MODE_CHANGE);
3429
3430 /* tell the bios a driver is loaded */
3431 bios_7_scratch |= RADEON_DRV_LOADED;
3432
3433 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
3434 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3435 WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch);
3436 }
3437
radeon_combios_output_lock(struct drm_encoder * encoder,bool lock)3438 void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock)
3439 {
3440 struct drm_device *dev = encoder->dev;
3441 struct radeon_device *rdev = dev->dev_private;
3442 uint32_t bios_6_scratch;
3443
3444 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3445
3446 if (lock)
3447 bios_6_scratch |= RADEON_DRIVER_CRITICAL;
3448 else
3449 bios_6_scratch &= ~RADEON_DRIVER_CRITICAL;
3450
3451 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3452 }
3453
3454 void
radeon_combios_connected_scratch_regs(struct drm_connector * connector,struct drm_encoder * encoder,bool connected)3455 radeon_combios_connected_scratch_regs(struct drm_connector *connector,
3456 struct drm_encoder *encoder,
3457 bool connected)
3458 {
3459 struct drm_device *dev = connector->dev;
3460 struct radeon_device *rdev = dev->dev_private;
3461 struct radeon_connector *radeon_connector =
3462 to_radeon_connector(connector);
3463 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3464 uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH);
3465 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3466
3467 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
3468 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
3469 if (connected) {
3470 DRM_DEBUG_KMS("TV1 connected\n");
3471 /* fix me */
3472 bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO;
3473 /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */
3474 bios_5_scratch |= RADEON_TV1_ON;
3475 bios_5_scratch |= RADEON_ACC_REQ_TV1;
3476 } else {
3477 DRM_DEBUG_KMS("TV1 disconnected\n");
3478 bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK;
3479 bios_5_scratch &= ~RADEON_TV1_ON;
3480 bios_5_scratch &= ~RADEON_ACC_REQ_TV1;
3481 }
3482 }
3483 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
3484 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
3485 if (connected) {
3486 DRM_DEBUG_KMS("LCD1 connected\n");
3487 bios_4_scratch |= RADEON_LCD1_ATTACHED;
3488 bios_5_scratch |= RADEON_LCD1_ON;
3489 bios_5_scratch |= RADEON_ACC_REQ_LCD1;
3490 } else {
3491 DRM_DEBUG_KMS("LCD1 disconnected\n");
3492 bios_4_scratch &= ~RADEON_LCD1_ATTACHED;
3493 bios_5_scratch &= ~RADEON_LCD1_ON;
3494 bios_5_scratch &= ~RADEON_ACC_REQ_LCD1;
3495 }
3496 }
3497 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
3498 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
3499 if (connected) {
3500 DRM_DEBUG_KMS("CRT1 connected\n");
3501 bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR;
3502 bios_5_scratch |= RADEON_CRT1_ON;
3503 bios_5_scratch |= RADEON_ACC_REQ_CRT1;
3504 } else {
3505 DRM_DEBUG_KMS("CRT1 disconnected\n");
3506 bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK;
3507 bios_5_scratch &= ~RADEON_CRT1_ON;
3508 bios_5_scratch &= ~RADEON_ACC_REQ_CRT1;
3509 }
3510 }
3511 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
3512 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
3513 if (connected) {
3514 DRM_DEBUG_KMS("CRT2 connected\n");
3515 bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR;
3516 bios_5_scratch |= RADEON_CRT2_ON;
3517 bios_5_scratch |= RADEON_ACC_REQ_CRT2;
3518 } else {
3519 DRM_DEBUG_KMS("CRT2 disconnected\n");
3520 bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK;
3521 bios_5_scratch &= ~RADEON_CRT2_ON;
3522 bios_5_scratch &= ~RADEON_ACC_REQ_CRT2;
3523 }
3524 }
3525 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
3526 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
3527 if (connected) {
3528 DRM_DEBUG_KMS("DFP1 connected\n");
3529 bios_4_scratch |= RADEON_DFP1_ATTACHED;
3530 bios_5_scratch |= RADEON_DFP1_ON;
3531 bios_5_scratch |= RADEON_ACC_REQ_DFP1;
3532 } else {
3533 DRM_DEBUG_KMS("DFP1 disconnected\n");
3534 bios_4_scratch &= ~RADEON_DFP1_ATTACHED;
3535 bios_5_scratch &= ~RADEON_DFP1_ON;
3536 bios_5_scratch &= ~RADEON_ACC_REQ_DFP1;
3537 }
3538 }
3539 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
3540 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
3541 if (connected) {
3542 DRM_DEBUG_KMS("DFP2 connected\n");
3543 bios_4_scratch |= RADEON_DFP2_ATTACHED;
3544 bios_5_scratch |= RADEON_DFP2_ON;
3545 bios_5_scratch |= RADEON_ACC_REQ_DFP2;
3546 } else {
3547 DRM_DEBUG_KMS("DFP2 disconnected\n");
3548 bios_4_scratch &= ~RADEON_DFP2_ATTACHED;
3549 bios_5_scratch &= ~RADEON_DFP2_ON;
3550 bios_5_scratch &= ~RADEON_ACC_REQ_DFP2;
3551 }
3552 }
3553 WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch);
3554 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3555 }
3556
3557 void
radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder * encoder,int crtc)3558 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
3559 {
3560 struct drm_device *dev = encoder->dev;
3561 struct radeon_device *rdev = dev->dev_private;
3562 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3563 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3564
3565 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
3566 bios_5_scratch &= ~RADEON_TV1_CRTC_MASK;
3567 bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT);
3568 }
3569 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3570 bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK;
3571 bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT);
3572 }
3573 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3574 bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK;
3575 bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT);
3576 }
3577 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3578 bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK;
3579 bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT);
3580 }
3581 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3582 bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK;
3583 bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT);
3584 }
3585 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3586 bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK;
3587 bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT);
3588 }
3589 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3590 }
3591
3592 void
radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder * encoder,bool on)3593 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
3594 {
3595 struct drm_device *dev = encoder->dev;
3596 struct radeon_device *rdev = dev->dev_private;
3597 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3598 uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3599
3600 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
3601 if (on)
3602 bios_6_scratch |= RADEON_TV_DPMS_ON;
3603 else
3604 bios_6_scratch &= ~RADEON_TV_DPMS_ON;
3605 }
3606 if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3607 if (on)
3608 bios_6_scratch |= RADEON_CRT_DPMS_ON;
3609 else
3610 bios_6_scratch &= ~RADEON_CRT_DPMS_ON;
3611 }
3612 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3613 if (on)
3614 bios_6_scratch |= RADEON_LCD_DPMS_ON;
3615 else
3616 bios_6_scratch &= ~RADEON_LCD_DPMS_ON;
3617 }
3618 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
3619 if (on)
3620 bios_6_scratch |= RADEON_DFP_DPMS_ON;
3621 else
3622 bios_6_scratch &= ~RADEON_DFP_DPMS_ON;
3623 }
3624 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3625 }
3626