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Searched refs:CG_SPLL_FUNC_CNTL (Results 1 – 23 of 23) sorted by relevance

/dragonfly/sys/dev/drm/radeon/
HDrv740d.h26 #define CG_SPLL_FUNC_CNTL 0x600 macro
HDrv730d.h26 #define CG_SPLL_FUNC_CNTL 0x600 macro
HDrs780d.h26 #define CG_SPLL_FUNC_CNTL 0x600 macro
HDrs780_dpm.c211 u32 fbdiv = (RREG32(CG_SPLL_FUNC_CNTL) & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT; in rs780_preset_starting_fbdiv()
986 u32 func_cntl = RREG32(CG_SPLL_FUNC_CNTL); in rs780_dpm_debugfs_print_current_performance_level()
1008 u32 func_cntl = RREG32(CG_SPLL_FUNC_CNTL); in rs780_dpm_get_current_sclk()
HDr600_dpm.c323 WREG32_P(CG_SPLL_FUNC_CNTL, SPLL_BYPASS_EN, ~SPLL_BYPASS_EN); in r600_enable_spll_bypass()
325 WREG32_P(CG_SPLL_FUNC_CNTL, 0, ~SPLL_BYPASS_EN); in r600_enable_spll_bypass()
333 if (RREG32(CG_SPLL_FUNC_CNTL) & SPLL_CHG_STATUS) in r600_wait_for_spll_change()
HDrv740_dpm.c290 RREG32(CG_SPLL_FUNC_CNTL); in rv740_read_clock_registers()
HDrv730_dpm.c203 RREG32(CG_SPLL_FUNC_CNTL); in rv730_read_clock_registers()
HDrv770d.h89 #define CG_SPLL_FUNC_CNTL 0x600 macro
HDsi.c3977 tmp = RREG32(CG_SPLL_FUNC_CNTL); in si_set_clk_bypass_mode()
3979 WREG32(CG_SPLL_FUNC_CNTL, tmp); in si_set_clk_bypass_mode()
4008 tmp = RREG32(CG_SPLL_FUNC_CNTL); in si_spll_powerdown()
4010 WREG32(CG_SPLL_FUNC_CNTL, tmp); in si_spll_powerdown()
4012 tmp = RREG32(CG_SPLL_FUNC_CNTL); in si_spll_powerdown()
4014 WREG32(CG_SPLL_FUNC_CNTL, tmp); in si_spll_powerdown()
HDnid.h538 #define CG_SPLL_FUNC_CNTL 0x600 macro
HDsid.h85 #define CG_SPLL_FUNC_CNTL 0x600 macro
HDcikd.h248 #define CG_SPLL_FUNC_CNTL 0xC0500140 macro
HDevergreend.h74 #define CG_SPLL_FUNC_CNTL 0x600 macro
HDr600d.h1270 #define CG_SPLL_FUNC_CNTL 0x600 macro
HDrv770_dpm.c1526 RREG32(CG_SPLL_FUNC_CNTL); in rv770_read_clock_registers()
HDni_dpm.c1183 ni_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL); in ni_read_clock_registers()
HDci_dpm.c1909 RREG32_SMC(CG_SPLL_FUNC_CNTL); in ci_read_clock_registers()
HDsi_dpm.c3570 si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL); in si_read_clock_registers()
/dragonfly/sys/dev/drm/amd/powerplay/smumgr/
HDiceland_smumgr.c826 CG_SPLL_FUNC_CNTL, SPLL_REF_DIV, dividers.uc_pll_ref_div); in iceland_calculate_sclk_params()
828 CG_SPLL_FUNC_CNTL, SPLL_PDIV_A, dividers.uc_pll_post_div); in iceland_calculate_sclk_params()
1461 … CG_SPLL_FUNC_CNTL, SPLL_PWRON, 0); in iceland_populate_smc_acpi_level()
1463 … CG_SPLL_FUNC_CNTL, SPLL_RESET, 1); in iceland_populate_smc_acpi_level()
HDfiji_smumgr.c897 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL, in fiji_calculate_sclk_params()
899 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL, in fiji_calculate_sclk_params()
1356 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL, in fiji_populate_smc_acpi_level()
1358 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL, in fiji_populate_smc_acpi_level()
HDtonga_smumgr.c559 CG_SPLL_FUNC_CNTL, SPLL_REF_DIV, dividers.uc_pll_ref_div); in tonga_calculate_sclk_params()
561 CG_SPLL_FUNC_CNTL, SPLL_PDIV_A, dividers.uc_pll_post_div); in tonga_calculate_sclk_params()
1200 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL, in tonga_populate_smc_acpi_level()
1202 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL, in tonga_populate_smc_acpi_level()
HDci_smumgr.c325 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL, in ci_calculate_sclk_params()
327 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL, in ci_calculate_sclk_params()
1413 … CG_SPLL_FUNC_CNTL, SPLL_PWRON, 0); in ci_populate_smc_acpi_level()
1415 … CG_SPLL_FUNC_CNTL, SPLL_RESET, 1); in ci_populate_smc_acpi_level()
/dragonfly/sys/dev/drm/amd/amdgpu/
HDsi_dpm.c4030 si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL); in si_read_clock_registers()