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Searched refs:CG_SCLK_DPM_CTRL_3 (Results 1 – 2 of 2) sorted by relevance

/dragonfly/sys/dev/drm/radeon/
HDsumo_dpm.c542 cg_sclk_dpm_ctrl_3 = RREG32(CG_SCLK_DPM_CTRL_3); in sumo_set_allos_gnb_slow()
546 WREG32(CG_SCLK_DPM_CTRL_3, cg_sclk_dpm_ctrl_3); in sumo_set_allos_gnb_slow()
604 if (RREG32(CG_SCLK_DPM_CTRL_3) & DPM_SCLK_ENABLE) in sumo_dpm_enabled()
612 WREG32_P(CG_SCLK_DPM_CTRL_3, DPM_SCLK_ENABLE, ~DPM_SCLK_ENABLE); in sumo_start_dpm()
617 WREG32_P(CG_SCLK_DPM_CTRL_3, 0, ~DPM_SCLK_ENABLE); in sumo_stop_dpm()
623 WREG32_P(CG_SCLK_DPM_CTRL_3, FORCE_SCLK_STATE_EN, ~FORCE_SCLK_STATE_EN); in sumo_set_forced_mode()
625 WREG32_P(CG_SCLK_DPM_CTRL_3, 0, ~FORCE_SCLK_STATE_EN); in sumo_set_forced_mode()
731 WREG32_P(CG_SCLK_DPM_CTRL_3, FORCE_SCLK_STATE(index), ~FORCE_SCLK_STATE_MASK); in sumo_set_forced_level()
945 u32 cg_sclk_dpm_ctrl_3 = RREG32(CG_SCLK_DPM_CTRL_3); in sumo_program_ttt()
951 WREG32(CG_SCLK_DPM_CTRL_3, cg_sclk_dpm_ctrl_3); in sumo_program_ttt()
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HDsumod.h231 #define CG_SCLK_DPM_CTRL_3 0x6e0 macro