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Searched refs:B3_RI_WTO_R2 (Results 1 – 2 of 2) sorted by relevance

/dragonfly/sys/dev/netif/msk/
HDif_mskreg.h512 #define B3_RI_WTO_R2 0x0196 /* 8 bit WR Timeout Queue R2 (TO6) */ macro
HDif_msk.c1251 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_R2), in mskc_reset()