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Searched refs:AR_PHY_CL_CAL_CTL (Results 1 – 4 of 4) sorted by relevance

/dragonfly/sys/dev/netif/ath/ath_hal/ar9002/
HDar9285_cal.c167 OS_REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE); in ar9285_hw_cl_cal()
169 OS_REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE); in ar9285_hw_cl_cal()
182 OS_REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE); in ar9285_hw_cl_cal()
183 OS_REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE); in ar9285_hw_cl_cal()
197 OS_REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE); in ar9285_hw_cl_cal()
/dragonfly/sys/dev/netif/ath/ath_hal/ar5416/
HDar5416phy.h366 #define AR_PHY_CL_CAL_CTL 0xA358 /* carrier leak cal control */ macro
/dragonfly/sys/contrib/dev/ath/ath_hal/ar9300/
HDar9300_reset.c3431 OS_REG_RMW_FIELD(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_MAP_HW_GEN, 0);
3576 OS_REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE); in ar9300_init_cal_internal()
3580 OS_REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE); in ar9300_init_cal_internal()
4854 ahp->tx_cl_cal_enable = (OS_REG_READ(ah, AR_PHY_CL_CAL_CTL) & in ar9300_reset()
HDar9300phy.h562 #define AR_PHY_CL_CAL_CTL AR_SM_OFFSET(BB_cl_cal_ctrl) macro