1 /*- 2 * Copyright (c) 2000 Doug Rabson 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: src/sys/pci/agpreg.h,v 1.19 2007/07/13 16:28:12 anholt Exp $ 27 * $DragonFly: src/sys/dev/agp/agpreg.h,v 1.7 2008/10/03 08:56:58 hasso Exp $ 28 */ 29 30 #ifndef _PCI_AGPREG_H_ 31 #define _PCI_AGPREG_H_ 32 33 /* 34 * Offsets for various AGP configuration registers. 35 */ 36 #define AGP_APBASE 0x10 37 #define AGP_CAPPTR 0x34 38 39 /* 40 * Offsets from the AGP Capability pointer. 41 */ 42 #define AGP_CAPID 0x0 43 #define AGP_CAPID_GET_MAJOR(x) (((x) & 0x00f00000U) >> 20) 44 #define AGP_CAPID_GET_MINOR(x) (((x) & 0x000f0000U) >> 16) 45 #define AGP_CAPID_GET_NEXT_PTR(x) (((x) & 0x0000ff00U) >> 8) 46 #define AGP_CAPID_GET_CAP_ID(x) (((x) & 0x000000ffU) >> 0) 47 48 #define AGP_STATUS 0x4 49 #define AGP_COMMAND 0x8 50 #define AGP_STATUS_AGP3 0x0008 51 #define AGP_STATUS_RQ_MASK 0xff000000 52 #define AGP_COMMAND_RQ_MASK 0xff000000 53 #define AGP_STATUS_ARQSZ_MASK 0xe000 54 #define AGP_COMMAND_ARQSZ_MASK 0xe000 55 #define AGP_STATUS_CAL_MASK 0x1c00 56 #define AGP_COMMAND_CAL_MASK 0x1c00 57 #define AGP_STATUS_ISOCH 0x10000 58 #define AGP_STATUS_ITA_COH 0x0100 59 #define AGP_STATUS_GART64 0x0080 60 #define AGP_STATUS_HTRANS 0x0040 61 #define AGP_STATUS_64BIT 0x0020 62 #define AGP_STATUS_FW 0x0010 63 #define AGP_COMMAND_RQ_MASK 0xff000000 64 #define AGP_COMMAND_ARQSZ_MASK 0xe000 65 #define AGP_COMMAND_CAL_MASK 0x1c00 66 #define AGP_COMMAND_AGP 0x0100 67 #define AGP_COMMAND_GART64 0x0080 68 #define AGP_COMMAND_64BIT 0x0020 69 #define AGP_COMMAND_FW 0x0010 70 71 /* 72 * Config offsets for Intel AGP chipsets. 73 */ 74 #define AGP_INTEL_NBXCFG 0x50 75 #define AGP_INTEL_ERRSTS 0x91 76 #define AGP_INTEL_AGPCTRL 0xb0 77 #define AGP_INTEL_APSIZE 0xb4 78 #define AGP_INTEL_ATTBASE 0xb8 79 80 /* 81 * Config offsets for Intel i8xx/E7xxx AGP chipsets. 82 */ 83 #define AGP_INTEL_MCHCFG 0x50 84 #define AGP_INTEL_I820_RDCR 0x51 85 #define AGP_INTEL_I845_AGPM 0x51 86 #define AGP_INTEL_I8XX_ERRSTS 0xc8 87 88 /* 89 * Config offsets for VIA AGP 2.x chipsets. 90 */ 91 #define AGP_VIA_GARTCTRL 0x80 92 #define AGP_VIA_APSIZE 0x84 93 #define AGP_VIA_ATTBASE 0x88 94 95 /* 96 * Config offsets for VIA AGP 3.0 chipsets. 97 */ 98 #define AGP3_VIA_GARTCTRL 0x90 99 #define AGP3_VIA_APSIZE 0x94 100 #define AGP3_VIA_ATTBASE 0x98 101 #define AGP_VIA_AGPSEL 0xfd 102 103 /* 104 * Config offsets for SiS AGP chipsets. 105 */ 106 #define AGP_SIS_ATTBASE 0x90 107 #define AGP_SIS_WINCTRL 0x94 108 #define AGP_SIS_TLBCTRL 0x97 109 #define AGP_SIS_TLBFLUSH 0x98 110 111 /* 112 * Config offsets for Ali AGP chipsets. 113 */ 114 #define AGP_ALI_AGPCTRL 0xb8 115 #define AGP_ALI_ATTBASE 0xbc 116 #define AGP_ALI_TLBCTRL 0xc0 117 118 /* 119 * Config offsets for the AMD 751 chipset. 120 */ 121 #define AGP_AMD751_APBASE 0x10 122 #define AGP_AMD751_REGISTERS 0x14 123 #define AGP_AMD751_APCTRL 0xac 124 #define AGP_AMD751_MODECTRL 0xb0 125 #define AGP_AMD751_MODECTRL_SYNEN 0x80 126 #define AGP_AMD751_MODECTRL2 0xb2 127 #define AGP_AMD751_MODECTRL2_G1LM 0x01 128 #define AGP_AMD751_MODECTRL2_GPDCE 0x02 129 #define AGP_AMD751_MODECTRL2_NGSE 0x08 130 131 /* 132 * Memory mapped register offsets for AMD 751 chipset. 133 */ 134 #define AGP_AMD751_CAPS 0x00 135 #define AGP_AMD751_CAPS_EHI 0x0800 136 #define AGP_AMD751_CAPS_P2P 0x0400 137 #define AGP_AMD751_CAPS_MPC 0x0200 138 #define AGP_AMD751_CAPS_VBE 0x0100 139 #define AGP_AMD751_CAPS_REV 0x00ff 140 #define AGP_AMD751_STATUS 0x02 141 #define AGP_AMD751_STATUS_P2PS 0x0800 142 #define AGP_AMD751_STATUS_GCS 0x0400 143 #define AGP_AMD751_STATUS_MPS 0x0200 144 #define AGP_AMD751_STATUS_VBES 0x0100 145 #define AGP_AMD751_STATUS_P2PE 0x0008 146 #define AGP_AMD751_STATUS_GCE 0x0004 147 #define AGP_AMD751_STATUS_VBEE 0x0001 148 #define AGP_AMD751_ATTBASE 0x04 149 #define AGP_AMD751_TLBCTRL 0x0c 150 151 /* 152 * Config registers for i810 device 0 153 */ 154 #define AGP_I810_SMRAM 0x70 155 #define AGP_I810_SMRAM_GMS 0xc0 156 #define AGP_I810_SMRAM_GMS_DISABLED 0x00 157 #define AGP_I810_SMRAM_GMS_ENABLED_0 0x40 158 #define AGP_I810_SMRAM_GMS_ENABLED_512 0x80 159 #define AGP_I810_SMRAM_GMS_ENABLED_1024 0xc0 160 #define AGP_I810_MISCC 0x72 161 #define AGP_I810_MISCC_WINSIZE 0x0001 162 #define AGP_I810_MISCC_WINSIZE_64 0x0000 163 #define AGP_I810_MISCC_WINSIZE_32 0x0001 164 #define AGP_I810_MISCC_PLCK 0x0008 165 #define AGP_I810_MISCC_PLCK_UNLOCKED 0x0000 166 #define AGP_I810_MISCC_PLCK_LOCKED 0x0008 167 #define AGP_I810_MISCC_WPTC 0x0030 168 #define AGP_I810_MISCC_WPTC_NOLIMIT 0x0000 169 #define AGP_I810_MISCC_WPTC_62 0x0010 170 #define AGP_I810_MISCC_WPTC_50 0x0020 171 #define AGP_I810_MISCC_WPTC_37 0x0030 172 #define AGP_I810_MISCC_RPTC 0x00c0 173 #define AGP_I810_MISCC_RPTC_NOLIMIT 0x0000 174 #define AGP_I810_MISCC_RPTC_62 0x0040 175 #define AGP_I810_MISCC_RPTC_50 0x0080 176 #define AGP_I810_MISCC_RPTC_37 0x00c0 177 178 /* 179 * Config registers for i810 device 1 180 */ 181 #define AGP_I810_GMADR 0x10 182 #define AGP_I810_MMADR 0x14 183 184 #define I810_PTE_VALID 0x00000001 185 186 /* 187 * Cache control 188 * 189 * Pre-Sandybridge bits 190 */ 191 #define I810_PTE_MAIN_UNCACHED 0x00000000 192 #define I810_PTE_LOCAL 0x00000002 /* Non-snooped main phys memory */ 193 #define I830_PTE_SYSTEM_CACHED 0x00000006 /* Snooped main phys memory */ 194 195 /* 196 * Memory mapped register offsets for i810 chipset. 197 */ 198 #define AGP_I810_PGTBL_CTL 0x2020 199 #define AGP_I810_PGTBL_ENABLED 0x00000001 200 /** 201 * This field determines the actual size of the global GTT on the 965 202 * and G33 203 */ 204 #define AGP_I810_PGTBL_SIZE_MASK 0x0000000e 205 #define AGP_I810_PGTBL_SIZE_512KB (0 << 1) 206 #define AGP_I810_PGTBL_SIZE_256KB (1 << 1) 207 #define AGP_I810_PGTBL_SIZE_128KB (2 << 1) 208 #define AGP_I810_PGTBL_SIZE_1MB (3 << 1) 209 #define AGP_I810_PGTBL_SIZE_2MB (4 << 1) 210 #define AGP_I810_PGTBL_SIZE_1_5MB (5 << 1) 211 #define AGP_G33_GCC1_SIZE_MASK (3 << 8) 212 #define AGP_G33_GCC1_SIZE_1M (1 << 8) 213 #define AGP_G33_GCC1_SIZE_2M (2 << 8) 214 #define AGP_G4x_GCC1_SIZE_MASK (0xf << 8) 215 #define AGP_G4x_GCC1_SIZE_1M (0x1 << 8) 216 #define AGP_G4x_GCC1_SIZE_2M (0x3 << 8) 217 #define AGP_G4x_GCC1_SIZE_VT_EN (0x8 << 8) 218 #define AGP_G4x_GCC1_SIZE_VT_1M \ 219 (AGP_G4x_GCC1_SIZE_1M | AGP_G4x_GCC1_SIZE_VT_EN) 220 #define AGP_G4x_GCC1_SIZE_VT_1_5M ((0x2 << 8) | AGP_G4x_GCC1_SIZE_VT_EN) 221 #define AGP_G4x_GCC1_SIZE_VT_2M \ 222 (AGP_G4x_GCC1_SIZE_2M | AGP_G4x_GCC1_SIZE_VT_EN) 223 224 #define AGP_I810_DRT 0x3000 225 #define AGP_I810_DRT_UNPOPULATED 0x00 226 #define AGP_I810_DRT_POPULATED 0x01 227 #define AGP_I810_GTT 0x10000 228 229 /* 230 * Config registers for i830MG device 0 231 */ 232 #define AGP_I830_GCC1 0x52 233 #define AGP_I830_GCC1_DEV2 0x08 234 #define AGP_I830_GCC1_DEV2_ENABLED 0x00 235 #define AGP_I830_GCC1_DEV2_DISABLED 0x08 236 #define AGP_I830_GCC1_GMS 0xf0 /* Top bit reserved pre-G33 */ 237 #define AGP_I830_GCC1_GMS_STOLEN_512 0x20 238 #define AGP_I830_GCC1_GMS_STOLEN_1024 0x30 239 #define AGP_I830_GCC1_GMS_STOLEN_8192 0x40 240 #define AGP_I830_GCC1_GMASIZE 0x01 241 #define AGP_I830_GCC1_GMASIZE_64 0x01 242 #define AGP_I830_GCC1_GMASIZE_128 0x00 243 #define AGP_I830_HIC 0x70 244 245 /* 246 * Config registers for 852GM/855GM/865G device 0 247 */ 248 #define AGP_I855_GCC1 0x52 249 #define AGP_I855_GCC1_DEV2 0x08 250 #define AGP_I855_GCC1_DEV2_ENABLED 0x00 251 #define AGP_I855_GCC1_DEV2_DISABLED 0x08 252 #define AGP_I855_GCC1_GMS 0xf0 /* Top bit reserved pre-G33 */ 253 #define AGP_I855_GCC1_GMS_STOLEN_0M 0x00 254 #define AGP_I855_GCC1_GMS_STOLEN_1M 0x10 255 #define AGP_I855_GCC1_GMS_STOLEN_4M 0x20 256 #define AGP_I855_GCC1_GMS_STOLEN_8M 0x30 257 #define AGP_I855_GCC1_GMS_STOLEN_16M 0x40 258 #define AGP_I855_GCC1_GMS_STOLEN_32M 0x50 259 260 /* 261 * 852GM/855GM variant identification 262 */ 263 #define AGP_I85X_CAPID 0x44 264 #define AGP_I85X_VARIANT_MASK 0x7 265 #define AGP_I85X_VARIANT_SHIFT 5 266 #define AGP_I855_GME 0x0 267 #define AGP_I855_GM 0x4 268 #define AGP_I852_GME 0x2 269 #define AGP_I852_GM 0x5 270 271 /* 272 * 915G registers 273 */ 274 #define AGP_I915_GMADR 0x18 275 #define AGP_I915_MMADR 0x10 276 #define AGP_I915_GTTADR 0x1C 277 #define AGP_I915_GCC1_GMS_STOLEN_48M 0x60 278 #define AGP_I915_GCC1_GMS_STOLEN_64M 0x70 279 #define AGP_I915_DEVEN 0x54 280 #define AGP_I915_DEVEN_D2F0 0x08 281 #define AGP_I915_DEVEN_D2F0_ENABLED 0x08 282 #define AGP_I915_DEVEN_D2F0_DISABLED 0x00 283 #define AGP_I915_MSAC 0x62 284 #define AGP_I915_MSAC_GMASIZE 0x02 285 #define AGP_I915_MSAC_GMASIZE_128 0x02 286 #define AGP_I915_MSAC_GMASIZE_256 0x00 287 #define AGP_I915_IFPADDR 0x60 288 289 /* 290 * G965 registers 291 */ 292 #define AGP_I965_GTTMMADR 0x10 293 #define AGP_I965_MSAC 0x62 294 #define AGP_I965_MSAC_GMASIZE_128 0x00 295 #define AGP_I965_MSAC_GMASIZE_256 0x02 296 #define AGP_I965_MSAC_GMASIZE_512 0x06 297 #define AGP_I965_PGTBL_SIZE_1MB (3 << 1) 298 #define AGP_I965_PGTBL_SIZE_2MB (4 << 1) 299 #define AGP_I965_PGTBL_SIZE_1_5MB (5 << 1) 300 #define AGP_I965_PGTBL_CTL2 0x20c4 301 #define AGP_I965_IFPADDR 0x70 302 303 /* 304 * G33 registers 305 */ 306 #define AGP_G33_MGGC_GGMS_MASK (3 << 8) 307 #define AGP_G33_MGGC_GGMS_SIZE_1M (1 << 8) 308 #define AGP_G33_MGGC_GGMS_SIZE_2M (2 << 8) 309 #define AGP_G33_GCC1_GMS_STOLEN_128M 0x80 310 #define AGP_G33_GCC1_GMS_STOLEN_256M 0x90 311 312 /* 313 * G4X registers 314 */ 315 #define AGP_G4X_GMADR 0x20 316 #define AGP_G4X_MMADR 0x10 317 #define AGP_G4X_GTTADR 0x18 318 #define AGP_G4X_GCC1_GMS_STOLEN_96M 0xa0 319 #define AGP_G4X_GCC1_GMS_STOLEN_160M 0xb0 320 #define AGP_G4X_GCC1_GMS_STOLEN_224M 0xc0 321 #define AGP_G4X_GCC1_GMS_STOLEN_352M 0xd0 322 323 /* 324 * NVIDIA nForce/nForce2 registers 325 */ 326 #define AGP_NVIDIA_0_APBASE 0x10 327 #define AGP_NVIDIA_0_APSIZE 0x80 328 #define AGP_NVIDIA_1_WBC 0xf0 329 #define AGP_NVIDIA_2_GARTCTRL 0xd0 330 #define AGP_NVIDIA_2_APBASE 0xd8 331 #define AGP_NVIDIA_2_APLIMIT 0xdc 332 #define AGP_NVIDIA_2_ATTBASE(i) (0xe0 + (i) * 4) 333 #define AGP_NVIDIA_3_APBASE 0x50 334 #define AGP_NVIDIA_3_APLIMIT 0x54 335 336 /* 337 * AMD64 GART registers 338 */ 339 #define AGP_AMD64_APCTRL 0x90 340 #define AGP_AMD64_APBASE 0x94 341 #define AGP_AMD64_ATTBASE 0x98 342 #define AGP_AMD64_CACHECTRL 0x9c 343 #define AGP_AMD64_APCTRL_GARTEN 0x00000001 344 #define AGP_AMD64_APCTRL_SIZE_MASK 0x0000000e 345 #define AGP_AMD64_APCTRL_DISGARTCPU 0x00000010 346 #define AGP_AMD64_APCTRL_DISGARTIO 0x00000020 347 #define AGP_AMD64_APCTRL_DISWLKPRB 0x00000040 348 #define AGP_AMD64_APBASE_MASK 0x00007fff 349 #define AGP_AMD64_ATTBASE_MASK 0xfffffff0 350 #define AGP_AMD64_CACHECTRL_INVGART 0x00000001 351 #define AGP_AMD64_CACHECTRL_PTEERR 0x00000002 352 353 /* 354 * NVIDIA nForce3 registers 355 */ 356 #define AGP_AMD64_NVIDIA_0_APBASE 0x10 357 #define AGP_AMD64_NVIDIA_1_APBASE1 0x50 358 #define AGP_AMD64_NVIDIA_1_APLIMIT1 0x54 359 #define AGP_AMD64_NVIDIA_1_APSIZE 0xa8 360 #define AGP_AMD64_NVIDIA_1_APBASE2 0xd8 361 #define AGP_AMD64_NVIDIA_1_APLIMIT2 0xdc 362 363 /* 364 * ULi M1689 registers 365 */ 366 #define AGP_AMD64_ULI_APBASE 0x10 367 #define AGP_AMD64_ULI_HTT_FEATURE 0x50 368 #define AGP_AMD64_ULI_ENU_SCR 0x54 369 370 /* 371 * ATI IGP registers 372 */ 373 #define ATI_GART_MMADDR 0x14 374 #define ATI_RS100_APSIZE 0xac 375 #define ATI_RS100_IG_AGPMODE 0xb0 376 #define ATI_RS300_APSIZE 0xf8 377 #define ATI_RS300_IG_AGPMODE 0xfc 378 #define ATI_GART_FEATURE_ID 0x00 379 #define ATI_GART_BASE 0x04 380 #define ATI_GART_CACHE_CNTRL 0x0c 381 382 #endif /* !_PCI_AGPREG_H_ */ 383