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Searched refs:ADDR_SURF_BANK_WIDTH_2 (Results 1 – 25 of 28) sorted by relevance

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/dragonfly/sys/dev/drm/amd/include/asic_reg/gmc/
HDgmc_8_2_enum.h959 ADDR_SURF_BANK_WIDTH_2 = 0x1, enumerator
HDgmc_8_1_enum.h1089 ADDR_SURF_BANK_WIDTH_2 = 0x1, enumerator
/dragonfly/sys/dev/drm/amd/include/asic_reg/bif/
HDbif_5_1_enum.h959 ADDR_SURF_BANK_WIDTH_2 = 0x1, enumerator
HDbif_5_0_enum.h1089 ADDR_SURF_BANK_WIDTH_2 = 0x1, enumerator
/dragonfly/sys/dev/drm/amd/include/asic_reg/smu/
HDsmu_8_0_enum.h959 ADDR_SURF_BANK_WIDTH_2 = 0x1, enumerator
HDsmu_7_1_0_enum.h1118 ADDR_SURF_BANK_WIDTH_2 = 0x1, enumerator
HDsmu_7_1_1_enum.h1119 ADDR_SURF_BANK_WIDTH_2 = 0x1, enumerator
HDsmu_7_1_3_enum.h1173 ADDR_SURF_BANK_WIDTH_2 = 0x1, enumerator
HDsmu_7_1_2_enum.h1137 ADDR_SURF_BANK_WIDTH_2 = 0x1, enumerator
/dragonfly/sys/dev/drm/amd/include/asic_reg/dce/
HDdce_8_0_enum.h1044 ADDR_SURF_BANK_WIDTH_2 = 0x1, enumerator
HDdce_10_0_enum.h1664 ADDR_SURF_BANK_WIDTH_2 = 0x1, enumerator
HDdce_11_0_enum.h5531 ADDR_SURF_BANK_WIDTH_2 = 0x1, enumerator
/dragonfly/sys/dev/drm/amd/include/asic_reg/uvd/
HDuvd_6_0_enum.h972 ADDR_SURF_BANK_WIDTH_2 = 0x1, enumerator
HDuvd_5_0_enum.h1102 ADDR_SURF_BANK_WIDTH_2 = 0x1, enumerator
/dragonfly/sys/dev/drm/amd/amdgpu/
HDgfx_v8_0.c2355 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in gfx_v8_0_tiling_mode_table_init()
2383 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in gfx_v8_0_tiling_mode_table_init()
2387 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in gfx_v8_0_tiling_mode_table_init()
2953 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in gfx_v8_0_tiling_mode_table_init()
2958 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in gfx_v8_0_tiling_mode_table_init()
3338 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in gfx_v8_0_tiling_mode_table_init()
3342 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in gfx_v8_0_tiling_mode_table_init()
3514 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in gfx_v8_0_tiling_mode_table_init()
3518 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in gfx_v8_0_tiling_mode_table_init()
/dragonfly/sys/dev/drm/amd/include/asic_reg/oss/
HDoss_2_4_enum.h1254 ADDR_SURF_BANK_WIDTH_2 = 0x1, enumerator
HDoss_3_0_1_enum.h1355 ADDR_SURF_BANK_WIDTH_2 = 0x1, enumerator
HDoss_3_0_enum.h1388 ADDR_SURF_BANK_WIDTH_2 = 0x1, enumerator
/dragonfly/sys/dev/drm/radeon/
HDsid.h1208 # define ADDR_SURF_BANK_WIDTH_2 1 macro
HDcik.c2860 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in cik_tiling_mode_table_init()
2864 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in cik_tiling_mode_table_init()
2975 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in cik_tiling_mode_table_init()
2979 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in cik_tiling_mode_table_init()
3011 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in cik_tiling_mode_table_init()
3015 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in cik_tiling_mode_table_init()
HDcikd.h1262 # define ADDR_SURF_BANK_WIDTH_2 1 macro
HDevergreend.h2219 # define ADDR_SURF_BANK_WIDTH_2 1 macro
HDsi.c2673 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in si_tiling_mode_table_init()
2888 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in si_tiling_mode_table_init()
/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
HDgfx_7_2_enum.h6201 ADDR_SURF_BANK_WIDTH_2 = 0x1, enumerator
HDgfx_8_1_enum.h6699 ADDR_SURF_BANK_WIDTH_2 = 0x1, enumerator

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