| /NextBSD/contrib/llvm/tools/clang/lib/CodeGen/ |
| HD | CGCall.h | 93 Writeback writeback; in addWriteback() local 94 writeback.Source = srcLV; in addWriteback() 95 writeback.Temporary = temporary; in addWriteback() 96 writeback.ToUse = toUse; in addWriteback() 97 Writebacks.push_back(writeback); in addWriteback()
|
| HD | CGCall.cpp | 2533 const CallArgList::Writeback &writeback) { in emitWriteback() argument 2534 const LValue &srcLV = writeback.Source; in emitWriteback() 2554 llvm::Value *value = CGF.Builder.CreateLoad(writeback.Temporary); in emitWriteback() 2568 if (writeback.ToUse) { in emitWriteback() 2576 CGF.EmitARCIntrinsicUse(writeback.ToUse); in emitWriteback()
|
| /NextBSD/contrib/gcc/config/arm/ |
| HD | arm1136jfs.md | 47 ;; and saturation stages. The fourth stage is writeback; see below. 50 ;; MAC1 through MAC3, and a fourth writeback stage. 52 ;; The 4th-stage writeback is shared between the ALU and MAC pipelines, 54 ;; moved into the writeback stage. Because the two pipelines operate 58 ;; data cache (2), and writeback stages. (Note that this pipeline, 59 ;; including the writeback stage, is independent from the ALU & LSU pipes.) 280 ;; the difference between operations with a base register writeback. 290 ;; Load byte results are not available until the writeback stage, where
|
| HD | vfp.md | 35 ;; - A 8-stage FMAC pipeline (7 execute + writeback) with forward from 38 ;; - A 5-stage DS pipeline (4 execute + writeback) for divide/sqrt insns. 41 ;; - A 4-stage LS pipeline (execute + 2 memory + writeback) with forward from
|
| HD | arm926ejs.md | 118 ;; the difference between operations with a base register writeback
|
| HD | arm1026ejs.md | 155 ;; the difference between operations with a base register writeback
|
| HD | arm1020e.md | 155 ;; the difference between operations with a base register writeback
|
| /NextBSD/usr.bin/mail/ |
| HD | quit.c | 185 writeback(rbuf); in quit() 294 writeback(rbuf); in quit() 335 writeback(FILE *res) in writeback() function
|
| HD | extern.h | 249 int writeback(FILE *);
|
| /NextBSD/sys/dev/virtio/block/ |
| HD | virtio_blk.h | 74 uint8_t writeback; member
|
| HD | virtio_blk.c | 1120 VTBLK_GET_CONFIG(dev, VIRTIO_BLK_F_CONFIG_WCE, writeback, blkcfg); in vtblk_read_config() 1327 offsetof(struct virtio_blk_config, writeback), wc); in vtblk_set_write_cache() 1342 wc = blkcfg->writeback; in vtblk_write_cache_enabled()
|
| /NextBSD/contrib/llvm/lib/Target/AArch64/ |
| HD | AArch64SchedCyclone.td | 61 // consumes the pipe for one cycle at issue and another cycle at writeback. 90 // but only consume the pipe for one cycle at issue and a cycle at writeback. 203 // The ID pipe is consumed for 2 cycles: issue and writeback. 210 // The ID pipe is consumed for 2 cycles: issue and writeback. 626 // Only the first WriteVLD and WriteAdr for writeback matches def operands. 767 // Only the WriteAdr for writeback matches a def operands.
|
| /NextBSD/contrib/llvm/lib/Target/ARM/Disassembler/ |
| HD | ARMDisassembler.cpp | 1533 bool writeback = (P == 0) || (W == 1); in DecodeAddrMode2IdxInstruction() local 1535 if (P && writeback) in DecodeAddrMode2IdxInstruction() 1537 else if (!P && writeback) in DecodeAddrMode2IdxInstruction() 1540 if (writeback && (Rn == 15 || Rn == Rt)) in DecodeAddrMode2IdxInstruction() 1640 bool writeback = (W == 1) | (P == 0); in DecodeAddrMode3Instruction() local 1662 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) in DecodeAddrMode3Instruction() 1676 if (writeback && (Rn == 15 || Rn == Rt)) in DecodeAddrMode3Instruction() 1693 if (!type && writeback && Rn == 15) in DecodeAddrMode3Instruction() 1695 if (writeback && (Rn == Rt || Rn == Rt2)) in DecodeAddrMode3Instruction() 1710 if (!type && writeback && (Rn == 15 || Rn == Rt)) in DecodeAddrMode3Instruction() [all …]
|
| /NextBSD/contrib/binutils/gas/config/ |
| HD | tc-arm.c | 344 unsigned writeback : 1; /* Operand has trailing ! */ member 4716 inst.operands[i].writeback = 1; in parse_address_main() 4743 inst.operands[i].writeback = 1; in parse_address_main() 5708 inst.operands[i].writeback = 1; in parse_operands() 5751 inst.operands[i].writeback = 1; in parse_operands() 5903 inst.operands[1].writeback = 1; in parse_operands() 6230 if (inst.operands[i].writeback) in encode_arm_addr_mode_common() 6236 assert (inst.operands[i].writeback); in encode_arm_addr_mode_common() 6334 assert (!inst.operands[i].writeback); in encode_arm_cp_address() 6348 if (inst.operands[i].writeback) in encode_arm_cp_address() [all …]
|
| /NextBSD/contrib/binutils/opcodes/ |
| HD | arm-dis.c | 3446 bfd_boolean writeback = FALSE, postind = FALSE; in print_insn_thumb32() local 3476 writeback = TRUE; in print_insn_thumb32() 3481 writeback = TRUE; in print_insn_thumb32() 3505 func (stream, writeback ? "]!" : "]"); in print_insn_thumb32()
|
| HD | ChangeLog | 100 * arm-dis.c (thumb32_opcodes): Display writeback ldrd/strd addresses.
|
| /NextBSD/contrib/llvm/lib/Target/ARM/ |
| HD | ARMScheduleA9.td | 448 // register file writeback!). 2313 // A9WriteAdr consumes AGU regardless address writeback. But it's 2323 // Store either has no def operands, or the one def for address writeback. 2341 // Load multiple with address writeback has an extra def operand in 2345 // resources are identical, For stores only the address writeback 2360 // Note: Unlike VLDM, VLD1 expects the writeback operand after the 2381 // address writeback.
|
| HD | ARMInstrNEON.td | 698 // ...with address register writeback: 854 // ...with address register writeback: 927 // ...with address register writeback: 986 // ...with address register writeback: 1111 // ...with address register writeback: 1174 // ...with address register writeback: 1245 // ...with address register writeback: 1322 // ...with address register writeback: 1409 // ...with address register writeback: 1484 // ...with address register writeback: [all …]
|
| HD | ARMInstrVFP.td | 128 let Inst{21} = 0; // No writeback 156 let Inst{21} = 0; // No writeback 251 let Inst{21} = 0; // No writeback
|
| HD | ARMInstrThumb2.td | 1717 let Inst{21} = 0; // No writeback 1747 let Inst{21} = 0; // No writeback 1786 let Inst{21} = 0; // No writeback 1822 let Inst{21} = 0; // No writeback
|
| HD | ARMInstrInfo.td | 3093 let Inst{21} = 0; // No writeback 3113 let Inst{21} = 0; // No writeback 3133 let Inst{21} = 0; // No writeback 3153 let Inst{21} = 0; // No writeback
|
| HD | ARMInstrThumb.td | 746 // There is no non-writeback version of STM for Thumb.
|
| /NextBSD/sys/netpfil/pf/ |
| HD | pf_norm.c | 1345 struct pf_state_peer *src, struct pf_state_peer *dst, int *writeback) in pf_normalize_tcp_stateful() argument 1458 *writeback = 1; in pf_normalize_tcp_stateful()
|
| /NextBSD/contrib/binutils/opcodes/po/ |
| HD | opcodes.pot | 70 msgid "address writeback not allowed"
|
| /NextBSD/contrib/binutils/gas/po/ |
| HD | gas.pot | 1919 msgid "instruction does not support writeback" 1956 msgid "writeback of base register is UNPREDICTABLE" 1960 msgid "writeback of base register when in register list is UNPREDICTABLE" 1964 msgid "if writeback register is in list, it must be the lowest reg in the list" 2041 msgid "writeback used in preload instruction" 2069 msgid "this addressing mode requires base-register writeback" 2113 msgid "Thumb does not support register indexing with writeback" 2125 msgid "cannot use writeback with PC-relative addressing" 2129 msgid "cannot use writeback with this instruction" 2371 msgid "writeback (!) must be used for VLDMDB and VSTMDB"
|