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/NextBSD/crypto/openssl/crypto/evp/
HDevptests.txt17 # AES 128 ECB tests (from FIPS-197 test vectors, encrypt)
21 # AES 192 ECB tests (from FIPS-197 test vectors, encrypt)
25 # AES 256 ECB tests (from FIPS-197 test vectors, encrypt)
29 # AES 128 ECB tests (from NIST test vectors, encrypt)
33 # AES 128 ECB tests (from NIST test vectors, decrypt)
37 # AES 192 ECB tests (from NIST test vectors, decrypt)
41 # AES 256 ECB tests (from NIST test vectors, decrypt)
45 # AES 128 CBC tests (from NIST test vectors, encrypt)
49 # AES 192 CBC tests (from NIST test vectors, encrypt)
53 # AES 256 CBC tests (from NIST test vectors, encrypt)
[all …]
/NextBSD/contrib/llvm/lib/Target/X86/
HDX86CallingConv.td43 // Boolean vectors of AVX-512 are returned in SIMD registers.
59 // 256-bit vectors are returned in YMM0 and XMM1, when they fit. YMM2 and YMM3
65 // 512-bit vectors are returned in ZMM0 and ZMM1, when they fit. ZMM2 and ZMM3
116 // 256-bit FP vectors
121 // 512-bit FP vectors
144 // 256-bit FP vectors
148 // 512-bit FP vectors
272 // Boolean vectors of AVX-512 are passed in SIMD registers.
313 // 256-bit vectors get 32-byte stack slots that are 32-byte aligned.
317 // 512-bit vectors get 64-byte stack slots that are 64-byte aligned.
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/NextBSD/sys/crypto/siphash/
HDsiphash_test.c39 uint8_t vectors[64][8] = variable
129 if (memcmp(out, vectors[i], 8)) in SipHash24_TestVectors()
/NextBSD/sys/dev/cxgbe/firmware/
HDt4fw_cfg.txt42 # PFs 0-3. These get 8 MSI/8 MSI-X vectors each. VFs are supported by
77 # It gets 32 MSI/128 MSI-X vectors.
105 # PF5 is the SCSI Controller PF. It gets 32 MSI/40 MSI-X vectors.
111 # PF6 is the FCoE Controller PF. It gets 32 MSI/40 MSI-X vectors.
HDt5fw_cfg.txt55 # PFs 0-3. These get 8 MSI/8 MSI-X vectors each. VFs are supported by
90 # It gets 32 MSI/128 MSI-X vectors.
118 # PF5 is the SCSI Controller PF. It gets 32 MSI/40 MSI-X vectors.
124 # PF6 is the FCoE Controller PF. It gets 32 MSI/40 MSI-X vectors.
/NextBSD/sys/dev/acpica/
HDacpi_hpet.c105 uint32_t vectors; member
496 t->vectors = bus_read_4(sc->mem_res, HPET_TIMER_CAP_CNF(i) + 4); in hpet_attach()
500 t->vectors, (t->caps & HPET_TCNF_INT_ROUTE) >> 9, in hpet_attach()
543 sc->t[0].vectors = 0; in hpet_attach()
544 sc->t[1].vectors = 0; in hpet_attach()
610 else if (dvectors & t->vectors) { in hpet_attach()
611 t->irq = ffs(dvectors & t->vectors) - 1; in hpet_attach()
634 if (t->irq < 0 && (cvectors & t->vectors) != 0) { in hpet_attach()
635 cvectors &= t->vectors; in hpet_attach()
713 else if (sc->irq >= 0 && (t->vectors & (1 << sc->irq))) in hpet_attach()
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/NextBSD/contrib/llvm/lib/Target/SystemZ/
HDSystemZCallingConv.td50 // Similarly for vectors, with V24 being the ABI-compliant choice.
51 // Sub-128 vectors are returned in the same way, but they're widened
80 // The first 8 named vector arguments are passed in V24-V31. Sub-128 vectors
88 // However, sub-128 vectors which need to go on the stack occupy just a
HDSystemZOperators.td625 // Arithmetic negation on vectors.
628 // Bitwise negation on vectors.
631 // Signed "integer greater than zero" on vectors.
634 // Signed "integer less than zero" on vectors.
637 // Integer absolute on vectors.
/NextBSD/contrib/wpa/src/crypto/
HDcrypto_module_tests.c351 } vectors[] = { in test_cbc() local
382 for (i = 0; i < ARRAY_SIZE(vectors); i++) { in test_cbc()
383 struct cbc_test_vector *tv = &vectors[i]; in test_cbc()
419 } vectors[] = { in test_ecb() local
472 for (i = 0; i < ARRAY_SIZE(vectors); i++) { in test_ecb()
473 struct ecb_test_vector *tv = &vectors[i]; in test_ecb()
/NextBSD/contrib/llvm/include/llvm/IR/
HDIntrinsicsPowerPC.td90 /// vectors and returns one. These intrinsics have no side effects.
97 /// vectors and returns one. These intrinsics have no side effects.
104 /// vectors and returns one. These intrinsics have no side effects.
111 /// vectors and returns one. These intrinsics have no side effects.
118 /// vectors and returns one. These intrinsics have no side effects.
125 /// vectors and returns one. These intrinsics have no side effects.
136 /// vectors and returns one. These intrinsics have no side effects.
143 /// vectors and returns one. These intrinsics have no side effects.
757 /// vectors and returns one. These intrinsics have no side effects.
764 /// vectors and returns one. These intrinsics have no side effects.
HDIntrinsicsARM.td186 // The table operands for VTBL and VTBX consist of 1 to 4 v8i8 vectors.
300 // The shift counts for these intrinsics are always vectors, even for constant
423 // Source operands are: the address, the N input vectors (since only one
443 // Source operands are: the address, the N vectors, and the alignment.
462 // Source operands are: the address, the N vectors, the lane number, and
HDInstruction.def172 HANDLE_OTHER_INST(56, ShuffleVector, ShuffleVectorInst) // shuffle two vectors.
/NextBSD/contrib/gcc/
HDmode-classes.def31 DEF_MODE_CLASS (MODE_VECTOR_INT), /* SIMD vectors */ \
/NextBSD/contrib/llvm/lib/Target/AArch64/
HDAArch64CallingConvention.td29 // Big endian vectors must be passed as if they were 1-element vectors so that
89 // Big endian vectors must be passed as if they were 1-element vectors so that
/NextBSD/contrib/llvm/lib/Target/Hexagon/
HDHexagonInstrInfoVector.td341 // Truncate: from vectors B and C copy all 'E'ven 'H'alf-word elements:
376 // Multiplies two v2i16 vectors: as Hexagon does not have a multiply
388 // Multiplies two v4i16 vectors.
397 // Multiplies two v4i8 vectors.
405 // Multiplies two v8i8 vectors.
/NextBSD/contrib/llvm/lib/Target/PowerPC/
HDPPCCallingConv.td59 // QPX vectors are returned in QF1 and QF2.
158 // QPX vectors that are stored in double precision need 32-byte alignment.
175 // QPX vectors mirror the scalar FP convention.
/NextBSD/sys/dev/pci/
HDvga_pci.c544 const u_int *vectors) in vga_pci_remap_msix() argument
551 return (pci_remap_msix(dev, count, vectors)); in vga_pci_remap_msix()
HDpcivar.h496 pci_remap_msix(device_t dev, int count, const u_int *vectors) in pci_remap_msix() argument
498 return (PCI_REMAP_MSIX(device_get_parent(dev), dev, count, vectors)); in pci_remap_msix()
HDpci_private.h101 int count, const u_int *vectors);
HDpci_if.m183 const u_int *vectors;
/NextBSD/sys/net/
HDiflib.c3886 int vectors, queues, queuemsgs, msgs; in iflib_msix_init() local
3961 vectors = queues + admincnt; in iflib_msix_init()
3962 if ((err = pci_alloc_msix(dev, &vectors)) == 0) { in iflib_msix_init()
3964 "Using MSIX interrupts with %d vectors\n", vectors); in iflib_msix_init()
3965 scctx->isc_vectors = vectors; in iflib_msix_init()
3968 return (vectors); in iflib_msix_init()
3970 device_printf(dev, "failed to allocate %d msix vectors, err: %d - using MSI\n", vectors, err); in iflib_msix_init()
3973 vectors = pci_msi_count(dev); in iflib_msix_init()
3975 scctx->isc_vectors = vectors; in iflib_msix_init()
3976 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) { in iflib_msix_init()
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/NextBSD/sys/dev/ntb/ntb_hw/
HDntb_hw.c880 u_int *vectors; in ntb_remap_msix() local
887 vectors = malloc(desired * sizeof(*vectors), M_NTB, M_ZERO | M_WAITOK); in ntb_remap_msix()
890 vectors[i] = (i % avail) + 1; in ntb_remap_msix()
892 rc = pci_remap_msix(dev, desired, vectors); in ntb_remap_msix()
893 free(vectors, M_NTB); in ntb_remap_msix()
/NextBSD/sys/arm/arm/
HDmachdep.c381 unsigned int *vectors = (int *) va; in arm_vector_init() local
382 unsigned int *vectors_data = vectors + (page0_data - page0); in arm_vector_init()
394 vectors[vec] = page0[vec]; in arm_vector_init()
/NextBSD/contrib/gcc/doc/
HDcfg.texi100 In addition to notes, the jump table vectors are also represented as
101 ``pseudo-instructions'' inside the insn stream. These vectors never
105 address and referencing the vector, so cleaning up these vectors is
106 postponed until after liveness analysis. Thus the jump table vectors
149 type point to type-safe vectors of edges to the predecessors and
/NextBSD/contrib/llvm/tools/clang/include/clang/Basic/
HDarm_neon.td138 // A concatenation of the high halves of the input vectors.
250 // 2,3,4: array of default vectors
678 // E.3.20 Combining vectors
682 // E.3.21 Splitting vectors
689 // E.3.22 Converting vectors
944 // Converting vectors
1026 // Converting vectors
1162 // Across vectors class

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