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Searched refs:v64i8 (Results 1 – 12 of 12) sorted by relevance

/NextBSD/contrib/llvm/include/llvm/CodeGen/
HDMachineValueType.h72 v64i8 = 25, // 64 x i8 enumerator
242 SimpleTy == MVT::v64i8 || SimpleTy == MVT::v32i16 || in is512BitVector()
297 case v64i8: return i8; in getVectorElementType()
338 case v64i8: return 64; in getVectorNumElements()
443 case v64i8: in getSizeInBits()
545 if (NumElements == 64) return MVT::v64i8; in getVectorVT()
HDValueTypes.td48 def v64i8 : ValueType<512, 25>; // 64 x i8 vector value
/NextBSD/contrib/llvm/lib/Target/X86/
HDX86CallingConv.td51 CCIfType<[v64i1], CCPromoteToType<v64i8>>,
68 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
149 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
280 CCIfType<[v64i1], CCPromoteToType<v64i8>>,
298 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
384 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
459 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
476 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
495 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
536 CCIfType<[v64i1], CCPromoteToType<v64i8>>,
[all …]
HDX86InstrAVX512.td361 def : Pat<(v8f64 (bitconvert (v64i8 VR512:$src))), (v8f64 VR512:$src)>;
366 def : Pat<(v16f32 (bitconvert (v64i8 VR512:$src))), (v16f32 VR512:$src)>;
370 def : Pat<(v8i64 (bitconvert (v64i8 VR512:$src))), (v8i64 VR512:$src)>;
376 def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>;
380 def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>;
384 def : Pat<(v64i8 (bitconvert (v8i64 VR512:$src))), (v64i8 VR512:$src)>;
385 def : Pat<(v64i8 (bitconvert (v16i32 VR512:$src))), (v64i8 VR512:$src)>;
386 def : Pat<(v64i8 (bitconvert (v32i16 VR512:$src))), (v64i8 VR512:$src)>;
387 def : Pat<(v64i8 (bitconvert (v8f64 VR512:$src))), (v64i8 VR512:$src)>;
388 def : Pat<(v64i8 (bitconvert (v16f32 VR512:$src))), (v64i8 VR512:$src)>;
HDX86RegisterInfo.td462 def VR512 : RegisterClass<"X86", [v16f32, v8f64, v64i8, v32i16, v16i32, v8i64], 512,
HDX86ISelLowering.cpp1500 addRegisterClass(MVT::v64i8, &X86::VR512RegClass); in X86TargetLowering()
1506 setOperationAction(ISD::LOAD, MVT::v64i8, Legal); in X86TargetLowering()
1510 setOperationAction(ISD::ADD, MVT::v64i8, Legal); in X86TargetLowering()
1512 setOperationAction(ISD::SUB, MVT::v64i8, Legal); in X86TargetLowering()
1526 setOperationAction(ISD::SIGN_EXTEND, MVT::v64i8, Custom); in X86TargetLowering()
1527 setOperationAction(ISD::ZERO_EXTEND, MVT::v64i8, Custom); in X86TargetLowering()
1531 setOperationAction(ISD::VSELECT, MVT::v64i8, Legal); in X86TargetLowering()
1535 setOperationAction(ISD::SMAX, MVT::v64i8, Legal); in X86TargetLowering()
1537 setOperationAction(ISD::UMAX, MVT::v64i8, Legal); in X86TargetLowering()
1539 setOperationAction(ISD::SMIN, MVT::v64i8, Legal); in X86TargetLowering()
[all …]
HDX86InstrFragmentsSIMD.td478 def loadv64i8 : PatFrag<(ops node:$ptr), (v64i8 (load node:$ptr))>;
/NextBSD/contrib/llvm/lib/IR/
HDValueTypes.cpp143 case MVT::v64i8: return "v64i8"; in getEVTString()
212 case MVT::v64i8: return VectorType::get(Type::getInt8Ty(Context), 64); in getTypeForEVT()
/NextBSD/contrib/llvm/lib/Target/AMDGPU/
HDSIRegisterInfo.td201 def SReg_512 : RegisterClass<"AMDGPU", [v64i8, v16i32], 512, (add SGPR_512)>;
HDSIISelLowering.cpp45 addRegisterClass(MVT::v64i8, &AMDGPU::SReg_512RegClass); in SITargetLowering()
/NextBSD/contrib/llvm/utils/TableGen/
HDCodeGenTarget.cpp85 case MVT::v64i8: return "MVT::v64i8"; in getEnumName()
/NextBSD/contrib/llvm/include/llvm/IR/
HDIntrinsics.td169 def llvm_v64i8_ty : LLVMType<v64i8>; // 64 x i8