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Searched refs:v32i8 (Results 1 – 17 of 17) sorted by relevance

/NextBSD/contrib/llvm/include/llvm/CodeGen/
HDMachineValueType.h71 v32i8 = 24, // 32 x i8 enumerator
235 SimpleTy == MVT::v32i8 || SimpleTy == MVT::v16i16 || in is256BitVector()
296 case v32i8: in getVectorElementType()
335 case v32i8: in getVectorNumElements()
437 case v32i8: in getSizeInBits()
544 if (NumElements == 32) return MVT::v32i8; in getVectorVT()
HDValueTypes.td47 def v32i8 : ValueType<256, 24>; // 32 x i8 vector value
/NextBSD/contrib/llvm/lib/Target/X86/
HDX86CallingConv.td50 CCIfType<[v32i1], CCPromoteToType<v32i8>>,
62 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
145 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
279 CCIfType<[v32i1], CCPromoteToType<v32i8>>,
292 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
314 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
338 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], CCPassIndirect<i64>>,
380 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
455 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
471 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
[all …]
HDX86TargetTransformInfo.cpp158 { ISD::SHL, MVT::v32i8, 11 }, // vpblendvb sequence. in getArithmeticInstrCost()
161 { ISD::SRL, MVT::v32i8, 11 }, // vpblendvb sequence. in getArithmeticInstrCost()
164 { ISD::SRA, MVT::v32i8, 24 }, // vpblendvb sequence. in getArithmeticInstrCost()
169 { ISD::SDIV, MVT::v32i8, 32*20 }, in getArithmeticInstrCost()
173 { ISD::UDIV, MVT::v32i8, 32*20 }, in getArithmeticInstrCost()
390 {ISD::VECTOR_SHUFFLE, MVT::v32i8, 9} in getShuffleCost()
696 { ISD::SETCC, MVT::v32i8, 4 }, in getCmpSelInstrCost()
703 { ISD::SETCC, MVT::v32i8, 1 }, in getCmpSelInstrCost()
HDX86InstrSSE.td352 def : Pat<(v16i8 (extract_subvector (v32i8 VR256:$src), (iPTR 0))),
353 (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src), sub_xmm))>;
369 (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
425 def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>;
429 def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
434 def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
436 def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>;
437 def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>;
438 def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>;
439 def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
[all …]
HDX86ISelLowering.cpp1040 addRegisterClass(MVT::v32i8, &X86::VR256RegClass); in X86TargetLowering()
1094 setOperationAction(ISD::SRL, MVT::v32i8, Custom); in X86TargetLowering()
1097 setOperationAction(ISD::SHL, MVT::v32i8, Custom); in X86TargetLowering()
1100 setOperationAction(ISD::SRA, MVT::v32i8, Custom); in X86TargetLowering()
1102 setOperationAction(ISD::SETCC, MVT::v32i8, Custom); in X86TargetLowering()
1124 setOperationAction(ISD::CTPOP, MVT::v32i8, Custom); in X86TargetLowering()
1142 setOperationAction(ISD::ADD, MVT::v32i8, Legal); in X86TargetLowering()
1147 setOperationAction(ISD::SUB, MVT::v32i8, Legal); in X86TargetLowering()
1152 setOperationAction(ISD::MUL, MVT::v32i8, Custom); in X86TargetLowering()
1159 setOperationAction(ISD::SMAX, MVT::v32i8, Legal); in X86TargetLowering()
[all …]
HDX86RegisterInfo.td448 def VR256 : RegisterClass<"X86", [v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
473 def VR256X : RegisterClass<"X86", [v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
HDX86InstrAVX512.td427 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
431 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
436 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
438 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
439 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
440 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
441 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
442 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
443 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
452 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
HDX86InstrFragmentsSIMD.td734 def bc_v32i8 : PatFrag<(ops node:$in), (v32i8 (bitconvert node:$in))>;
/NextBSD/contrib/llvm/lib/IR/
HDValueTypes.cpp142 case MVT::v32i8: return "v32i8"; in getEVTString()
211 case MVT::v32i8: return VectorType::get(Type::getInt8Ty(Context), 32); in getTypeForEVT()
/NextBSD/contrib/llvm/lib/Target/X86/InstPrinter/
HDX86InstComments.cpp324 DecodePSLLDQMask(MVT::v32i8, in EmitAnyX86InstComments()
343 DecodePSRLDQMask(MVT::v32i8, in EmitAnyX86InstComments()
368 DecodePALIGNRMask(MVT::v32i8, in EmitAnyX86InstComments()
457 DecodeUNPCKHMask(MVT::v32i8, ShuffleMask); in EmitAnyX86InstComments()
546 DecodeUNPCKLMask(MVT::v32i8, ShuffleMask); in EmitAnyX86InstComments()
/NextBSD/contrib/llvm/lib/Target/AMDGPU/
HDSIRegisterInfo.td199 def SReg_256 : RegisterClass<"AMDGPU", [v32i8, v8i32, v8f32], 256, (add SGPR_256)>;
212 def VReg_256 : RegisterClass<"AMDGPU", [v32i8, v8i32, v8f32], 256, (add VGPR_256)>;
HDSIInstructions.td2122 defm : SMRD_Pattern <S_LOAD_DWORDX8_IMM, S_LOAD_DWORDX8_SGPR, v32i8>;
2132 defm : SMRD_Pattern_vi <S_LOAD_DWORDX8_IMM, S_LOAD_DWORDX8_SGPR, v32i8>;
2356 (SIsample i32:$addr, v32i8:$rsrc, v4i32:$sampler, imm),
2361 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, imm),
2366 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, TEX_RECT),
2371 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, TEX_ARRAY),
2377 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, TEX_SHADOW),
2383 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, TEX_SHADOW_ARRAY),
2436 (name addr_type:$addr, v32i8:$rsrc, imm),
2441 (name addr_type:$addr, v32i8:$rsrc, TEX_ARRAY),
[all …]
HDSIISelLowering.cpp44 addRegisterClass(MVT::v32i8, &AMDGPU::SReg_256RegClass); in SITargetLowering()
HDSIInstrInfo.td114 SDTypeProfile<1, 4, [SDTCisVT<0, v4f32>, SDTCisVT<2, v32i8>,
/NextBSD/contrib/llvm/utils/TableGen/
HDCodeGenTarget.cpp84 case MVT::v32i8: return "MVT::v32i8"; in getEnumName()
/NextBSD/contrib/llvm/include/llvm/IR/
HDIntrinsics.td168 def llvm_v32i8_ty : LLVMType<v32i8>; // 32 x i8