| /NextBSD/contrib/llvm/include/llvm/CodeGen/ |
| HD | MachineValueType.h | 102 v1f64 = 51, // 1 x f64 enumerator
221 SimpleTy == MVT::v1f64); in is64BitVector()
323 case v1f64: in getVectorElementType()
375 case v1f64: return 1; in getVectorNumElements()
424 case v1f64: return 64; in getSizeInBits()
585 if (NumElements == 1) return MVT::v1f64; in getVectorVT()
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| HD | ValueTypes.td | 75 def v1f64 : ValueType<64, 51>; // 1 x f64 vector value
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| /NextBSD/contrib/llvm/lib/Target/AArch64/ |
| HD | AArch64ISelDAGToDAG.cpp | 2414 else if (VT == MVT::v1i64 || VT == MVT::v1f64) in Select()
2432 else if (VT == MVT::v1i64 || VT == MVT::v1f64) in Select()
2450 else if (VT == MVT::v1i64 || VT == MVT::v1f64) in Select()
2468 else if (VT == MVT::v1i64 || VT == MVT::v1f64) in Select()
2486 else if (VT == MVT::v1i64 || VT == MVT::v1f64) in Select()
2504 else if (VT == MVT::v1i64 || VT == MVT::v1f64) in Select()
2522 else if (VT == MVT::v1i64 || VT == MVT::v1f64) in Select()
2540 else if (VT == MVT::v1i64 || VT == MVT::v1f64) in Select()
2558 else if (VT == MVT::v1i64 || VT == MVT::v1f64) in Select()
2573 VT == MVT::v1f64) in Select()
[all …]
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| HD | AArch64InstrInfo.td | 1346 defm : VecROLoadPat<ro64, v1f64, LDRDroW, LDRDroX>;
1489 def : Pat<(v1f64 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1650 def : Pat<(v1f64 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1971 defm : VecROStorePat<ro64, v1f64, FPR64, STRDroW, STRDroX>;
2064 def : Pat<(store (v1f64 FPR64:$Rt),
2161 def : Pat<(store (v1f64 FPR64:$Rt), (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2267 def : Pat<(pre_store (v1f64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2321 def : Pat<(post_store (v1f64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2466 def : Pat<(v1f64 (int_aarch64_neon_frintn (v1f64 FPR64:$Rn))),
2501 def : Pat<(v1f64 (AArch64fmax (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
[all …]
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| HD | AArch64CallingConvention.td | 70 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16],
79 CCIfType<[i64, f64, v1f64, v2f32, v1i64, v2i32, v4i16, v8i8, v4f16],
106 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16],
151 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16],
161 CCIfType<[i64, f64, v1f64, v2f32, v1i64, v2i32, v4i16, v8i8, v4f16],
180 CCIfType<[i64, f64, v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16],
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| HD | AArch64ISelLowering.cpp | 110 addDRTypeForNEON(MVT::v1f64); in AArch64TargetLowering()
522 setOperationAction(ISD::FABS, MVT::v1f64, Expand); in AArch64TargetLowering()
523 setOperationAction(ISD::FADD, MVT::v1f64, Expand); in AArch64TargetLowering()
524 setOperationAction(ISD::FCEIL, MVT::v1f64, Expand); in AArch64TargetLowering()
525 setOperationAction(ISD::FCOPYSIGN, MVT::v1f64, Expand); in AArch64TargetLowering()
526 setOperationAction(ISD::FCOS, MVT::v1f64, Expand); in AArch64TargetLowering()
527 setOperationAction(ISD::FDIV, MVT::v1f64, Expand); in AArch64TargetLowering()
528 setOperationAction(ISD::FFLOOR, MVT::v1f64, Expand); in AArch64TargetLowering()
529 setOperationAction(ISD::FMA, MVT::v1f64, Expand); in AArch64TargetLowering()
530 setOperationAction(ISD::FMUL, MVT::v1f64, Expand); in AArch64TargetLowering()
[all …]
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| HD | AArch64RegisterInfo.td | 396 def FPR64 : RegisterClass<"AArch64", [f64, i64, v2f32, v1f64, v8i8, v4i16, v2i32,
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| HD | AArch64InstrFormats.td | 5416 def : Pat<(v1f64 (OpNode (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
5429 def : Pat<(v1i64 (OpNode (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
5575 def : Pat<(v1i64 (OpNode (v1f64 FPR64:$Rn))),
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| /NextBSD/contrib/llvm/lib/IR/ |
| HD | ValueTypes.cpp | 169 case MVT::v1f64: return "v1f64"; in getEVTString()
238 case MVT::v1f64: return VectorType::get(Type::getDoubleTy(Context), 1); in getTypeForEVT()
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| /NextBSD/contrib/llvm/utils/TableGen/ |
| HD | CodeGenTarget.cpp | 111 case MVT::v1f64: return "MVT::v1f64"; in getEnumName()
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| /NextBSD/contrib/llvm/include/llvm/IR/ |
| HD | Intrinsics.td | 199 def llvm_v1f64_ty : LLVMType<v1f64>; // 1 x double
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