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Searched refs:v16i32 (Results 1 – 18 of 18) sorted by relevance

/NextBSD/contrib/llvm/include/llvm/CodeGen/
HDMachineValueType.h83 v16i32 = 36, // 16 x i32 enumerator
243 SimpleTy == MVT::v8i64 || SimpleTy == MVT::v16i32); in is512BitVector()
308 case v16i32: return i32; in getVectorElementType()
342 case v16i32: in getVectorNumElements()
445 case v16i32: in getSizeInBits()
560 if (NumElements == 16) return MVT::v16i32; in getVectorVT()
HDValueTypes.td59 def v16i32 : ValueType<512, 36>; // 16 x i32 vector value
/NextBSD/contrib/llvm/lib/Target/X86/
HDX86TargetTransformInfo.cpp136 { ISD::SHL, MVT::v16i32, 1 }, in getArithmeticInstrCost()
137 { ISD::SRL, MVT::v16i32, 1 }, in getArithmeticInstrCost()
138 { ISD::SRA, MVT::v16i32, 1 }, in getArithmeticInstrCost()
511 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 1 }, in getCastInstrCost()
512 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 1 }, in getCastInstrCost()
515 { ISD::TRUNCATE, MVT::v16i32, MVT::v8i64, 4 }, in getCastInstrCost()
518 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, in getCastInstrCost()
519 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, in getCastInstrCost()
521 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, in getCastInstrCost()
522 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, in getCastInstrCost()
[all …]
HDX86CallingConv.td68 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
122 CCIfType<[v16f32, v8f64, v16i32, v8i64],
149 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
298 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
318 CCIfType<[v16i32, v8i64, v16f32, v8f64],
341 CCIfType<[v16i32, v16f32, v8f64, v8i64], CCPassIndirect<i64>>,
384 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
459 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
476 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
495 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
[all …]
HDX86InstrAVX512.td55 // Size of the element type in bits, e.g. 32 for v16i32.
83 !if (!eq (EltSize, 64), "v8i64", "v16i32"),
88 // The corresponding float type, e.g. v16f32 for v16i32
359 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
364 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
368 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
373 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
374 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
375 def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>;
376 def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>;
[all …]
HDX86InstrFragmentsSIMD.td480 def loadv16i32 : PatFrag<(ops node:$ptr), (v16i32 (load node:$ptr))>;
562 (v16i32 (alignedload512 node:$ptr))>;
673 return (Mgt->getIndex().getValueType() == MVT::v16i32 ||
674 Mgt->getBasePtr().getValueType() == MVT::v16i32);
720 return (Sc->getIndex().getValueType() == MVT::v16i32 ||
721 Sc->getBasePtr().getValueType() == MVT::v16i32);
741 def bc_v16i32 : PatFrag<(ops node:$in), (v16i32 (bitconvert node:$in))>;
HDX86ISelLowering.cpp1269 addRegisterClass(MVT::v16i32, &X86::VR512RegClass); in X86TargetLowering()
1281 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i8, Legal); in X86TargetLowering()
1282 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i8, Legal); in X86TargetLowering()
1283 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i16, Legal); in X86TargetLowering()
1284 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i16, Legal); in X86TargetLowering()
1305 setOperationAction(ISD::LOAD, MVT::v16i32, Legal); in X86TargetLowering()
1334 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal); in X86TargetLowering()
1335 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal); in X86TargetLowering()
1338 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal); in X86TargetLowering()
1343 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal); in X86TargetLowering()
[all …]
HDX86RegisterInfo.td462 def VR512 : RegisterClass<"X86", [v16f32, v8f64, v64i8, v32i16, v16i32, v8i64], 512,
/NextBSD/contrib/llvm/lib/Target/ARM/
HDARMTargetTransformInfo.cpp97 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 6 }, in getCastInstrCost()
98 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 6 }, in getCastInstrCost()
101 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 6 }, in getCastInstrCost()
126 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 4 }, in getCastInstrCost()
127 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 4 }, in getCastInstrCost()
279 { ISD::SELECT, MVT::v16i1, MVT::v16i32, 4*16 + 1*6 + 1*8 + 1*4 }, in getCmpSelInstrCost()
/NextBSD/contrib/llvm/lib/IR/
HDValueTypes.cpp154 case MVT::v16i32: return "v16i32"; in getEVTString()
223 case MVT::v16i32: return VectorType::get(Type::getInt32Ty(Context), 16); in getTypeForEVT()
/NextBSD/contrib/llvm/lib/Target/AMDGPU/
HDSIRegisterInfo.td201 def SReg_512 : RegisterClass<"AMDGPU", [v64i8, v16i32], 512, (add SGPR_512)>;
214 def VReg_512 : RegisterClass<"AMDGPU", [v16i32, v16f32], 512, (add VGPR_512)>;
HDSIISelLowering.cpp60 addRegisterClass(MVT::v16i32, &AMDGPU::SReg_512RegClass); in SITargetLowering()
67 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i32, Expand); in SITargetLowering()
85 setOperationAction(ISD::LOAD, MVT::v16i32, Custom); in SITargetLowering()
88 setOperationAction(ISD::STORE, MVT::v16i32, Custom); in SITargetLowering()
160 setTruncStoreAction(MVT::v16i32, MVT::v16i8, Expand); in SITargetLowering()
161 setTruncStoreAction(MVT::v16i32, MVT::v16i16, Expand); in SITargetLowering()
178 for (MVT VT : {MVT::v8i32, MVT::v8f32, MVT::v16i32, MVT::v16f32}) { in SITargetLowering()
HDSIInstructions.td2124 defm : SMRD_Pattern <S_LOAD_DWORDX16_IMM, S_LOAD_DWORDX16_SGPR, v16i32>;
2134 defm : SMRD_Pattern_vi <S_LOAD_DWORDX16_IMM, S_LOAD_DWORDX16_SGPR, v16i32>;
2239 def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V16), v16i32>;
2432 v16i32>;
2541 i32, v16i32, Index, !cast<SubRegIndex>(sub#Index)
2544 i32, v16i32, Index, !cast<SubRegIndex>(sub#Index)
2585 def : BitConvert <v16i32, v16f32, VReg_512>;
2586 def : BitConvert <v16f32, v16i32, VReg_512>;
3105 defm : SI_INDIRECT_Pattern <v16i32, i32, SI_INDIRECT_DST_V16>;
HDAMDGPUISelLowering.cpp160 AddPromotedToType(ISD::STORE, MVT::v16f32, MVT::v16i32); in AMDGPUTargetLowering()
200 AddPromotedToType(ISD::LOAD, MVT::v16f32, MVT::v16i32); in AMDGPUTargetLowering()
/NextBSD/contrib/llvm/lib/Target/X86/InstPrinter/
HDX86InstComments.cpp501 DecodeUNPCKHMask(MVT::v16i32, ShuffleMask); in EmitAnyX86InstComments()
590 DecodeUNPCKLMask(MVT::v16i32, ShuffleMask); in EmitAnyX86InstComments()
/NextBSD/contrib/llvm/lib/Target/AArch64/
HDAArch64TargetTransformInfo.cpp361 { ISD::SELECT, MVT::v16i1, MVT::v16i32, 16 * AmortizationCost }, in getCmpSelInstrCost()
/NextBSD/contrib/llvm/utils/TableGen/
HDCodeGenTarget.cpp96 case MVT::v16i32: return "MVT::v16i32"; in getEnumName()
/NextBSD/contrib/llvm/include/llvm/IR/
HDIntrinsics.td182 def llvm_v16i32_ty : LLVMType<v16i32>; // 16 x i32