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Searched refs:setReg (Results 1 – 25 of 61) sorted by relevance

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/NextBSD/contrib/llvm/lib/Target/PowerPC/
HDPPCVSXFMAMutate.cpp229 MI->getOperand(0).setReg(KilledProdReg); in processBlock()
230 MI->getOperand(1).setReg(KilledProdReg); in processBlock()
231 MI->getOperand(3).setReg(AddReg); in processBlock()
232 MI->getOperand(2).setReg(OtherProdReg); in processBlock()
266 UseMO.setReg(KilledProdReg); in processBlock()
HDPPCVSXCopy.cpp116 SrcMO.setReg(NewVReg); in processBlock()
136 SrcMO.setReg(NewVReg); in processBlock()
HDPPCVSXSwapRemoval.cpp803 MI->getOperand(1).setReg(Reg2); in handleSpecialSwappables()
804 MI->getOperand(2).setReg(Reg1); in handleSpecialSwappables()
824 MI->getOperand(0).setReg(NewVReg); in handleSpecialSwappables()
/NextBSD/contrib/llvm/lib/Target/Hexagon/
HDHexagonPeephole.cpp257 MI->getOperand(0).setReg(PeepholeSrc); in runOnMachineFunction()
287 MI->getOperand(PR).setReg(POrig); in runOnMachineFunction()
310 Dst.setReg(Src.getReg()); in ChangeOpInto()
HDHexagonHardwareLoops.cpp1066 UseMI->getOperand(0).setReg(0U); in removeIfDead()
1556 MO.setReg(NewR); in setImmediate()
1757 IndMO->setReg(I->first); in fixupInductionVariable()
1758 nonIndMO->setReg(nonIndI->getOperand(1).getReg()); in fixupInductionVariable()
1800 MO.setReg(I->first); in fixupInductionVariable()
/NextBSD/contrib/llvm/lib/Target/Sparc/
HDDelaySlotFiller.cpp380 AddMI->getOperand(0).setReg(reg - SP::I0 + SP::O0); in combineRestoreADD()
419 OrMI->getOperand(0).setReg(reg - SP::I0 + SP::O0); in combineRestoreOR()
453 RestoreMI->getOperand(0).setReg(reg - SP::I0 + SP::O0); in combineRestoreSETHIi()
454 RestoreMI->getOperand(1).setReg(SP::G0); in combineRestoreSETHIi()
HDSparcRegisterInfo.cpp188 MI.getOperand(2).setReg(SrcOddReg); in eliminateFrameIndex()
201 MI.getOperand(0).setReg(DestOddReg); in eliminateFrameIndex()
/NextBSD/contrib/llvm/lib/Target/AMDGPU/
HDSIPrepareScratchRegs.cpp180 MI.getOperand(2).setReg(ScratchRsrcReg); in runOnMachineFunction()
183 MI.getOperand(3).setReg(ScratchOffsetReg); in runOnMachineFunction()
HDR600EmitClauseMarkers.cpp165 Consts[i].first->setReg( in SubstituteKCacheBank()
169 Consts[i].first->setReg( in SubstituteKCacheBank()
HDR600InstrInfo.cpp978 MO2.setReg(AMDGPU::PRED_SEL_ONE); in ReverseBranchCondition()
981 MO2.setReg(AMDGPU::PRED_SEL_ZERO); in ReverseBranchCondition()
1015 .setReg(Pred[2].getReg()); in PredicateInstruction()
1017 .setReg(Pred[2].getReg()); in PredicateInstruction()
1019 .setReg(Pred[2].getReg()); in PredicateInstruction()
1021 .setReg(Pred[2].getReg()); in PredicateInstruction()
1029 PMO.setReg(Pred[2].getReg()); in PredicateInstruction()
1290 .setReg(MO.getReg()); in buildSlotOfVectorInstruction()
HDR600ExpandSpecialInstrs.cpp88 DstOp.setReg(AMDGPU::OQAP); in runOnMachineFunction()
94 Mov->getOperand(MovPredSelIdx).setReg( in runOnMachineFunction()
HDR600ControlFlowFinalizer.cpp360 Srcs[i].first->setReg(LiteralRegs[Index]); in getLiteral()
363 Srcs[i].first->setReg(LiteralRegs[Lits.size()]); in getLiteral()
/NextBSD/contrib/llvm/lib/CodeGen/
HDAntiDepBreaker.h61 MI->getOperand(0).setReg(NewReg); in UpdateDbgValue()
HDPeepholeOptimizer.cpp452 UseMO->setReg(NewVR); in INITIALIZE_PASS_DEPENDENCY()
661 MOSrc.setReg(NewReg); in RewriteCurrentSource()
712 MO.setReg(NewReg); in RewriteCurrentSource()
761 CopyLike.getOperand(CurrentSrcIdx).setReg(NewReg); in RewriteCurrentSource()
842 MO.setReg(NewReg); in RewriteCurrentSource()
HDTargetInstrInfo.cpp171 MI->getOperand(0).setReg(Reg0); in commuteInstruction()
174 MI->getOperand(Idx2).setReg(Reg1); in commuteInstruction()
175 MI->getOperand(Idx1).setReg(Reg2); in commuteInstruction()
238 MO.setReg(Pred[j].getReg()); in PredicateInstruction()
HDTailDuplication.cpp444 MO.setReg(NewReg); in DuplicateInstruction()
451 MO.setReg(VI->second); in DuplicateInstruction()
520 II->getOperand(Idx).setReg(SrcReg); in UpdateSuccessorsPHIs()
532 II->getOperand(Idx).setReg(Reg); in UpdateSuccessorsPHIs()
HDMachineRegisterInfo.cpp297 O.setReg(ToReg); in replaceRegWith()
442 UseMI->getOperand(0).setReg(0U); in markUsesInDebugValueAsUndef()
HDRegAllocFast.cpp678 MO.setReg(PhysReg); in setPhysReg()
683 MO.setReg(PhysReg ? TRI->getSubReg(PhysReg, MO.getSubReg()) : 0); in setPhysReg()
866 MO.setReg(0); in AllocateBasicBlock()
/NextBSD/contrib/llvm/lib/Target/Mips/
HDMipsOptimizePICCall.cpp138 I->getOperand(0).setReg(DstReg); in setCallTargetReg()
229 getCallTargetRegOpnd(*I)->setReg(getReg(Entry)); in visitNode()
/NextBSD/contrib/llvm/lib/Target/SystemZ/
HDSystemZShortenInst.cpp93 MI.getOperand(0).setReg(SystemZMC::getRegAsGR64(Reg)); in shortenIIF()
98 MI.getOperand(0).setReg(SystemZMC::getRegAsGR64(Reg)); in shortenIIF()
/NextBSD/contrib/llvm/lib/Target/AArch64/
HDAArch64DeadRegisterDefinitionsPass.cpp111 MO.setReg(NewReg); in processMachineBasicBlock()
HDAArch64A57FPLoadBalancing.cpp569 U.setReg(Substs[OrigReg]); in colorChain()
595 MO.setReg(Reg); in colorChain()
/NextBSD/contrib/llvm/include/llvm/MC/
HDMCInst.h69 void setReg(unsigned Reg) { in setReg() function
/NextBSD/contrib/llvm/projects/libunwind/src/
HDUnwindCursor.hpp381 virtual void setReg(int, unw_word_t) { in setReg() function in libunwind::AbstractUnwindCursor
426 virtual void setReg(int, unw_word_t);
605 void UnwindCursor<A, R>::setReg(int regNum, unw_word_t value) { in setReg() function in libunwind::UnwindCursor
1320 setReg(UNW_REG_SP, getReg(UNW_REG_SP) + _info.gp); in step()
HDlibunwind.cpp183 co->setReg(regNum, (pint_t)value); in unw_set_reg()

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