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Searched refs:rx_base (Results 1 – 15 of 15) sorted by relevance

/NextBSD/sys/dev/sfxge/common/
HDsiena_sram.c46 uint32_t rx_base, tx_base; in siena_sram_init() local
51 rx_base = encp->enc_buftbl_limit; in siena_sram_init()
52 tx_base = rx_base + (encp->enc_rxq_limit * in siena_sram_init()
63 EFX_POPULATE_OWORD_1(oword, FRF_AZ_SRM_RX_DC_BASE_ADR, rx_base); in siena_sram_init()
/NextBSD/sys/dev/netmap/
HDif_igb_netmap.h224 union e1000_adv_rx_desc *curr = &rxr->rx_base[nic_i]; in igb_netmap_rxsync()
254 union e1000_adv_rx_desc *curr = &rxr->rx_base[nic_i]; in igb_netmap_rxsync()
HDif_em_netmap.h242 union e1000_rx_desc_extended *curr = &rxr->rx_base[nic_i]; in em_netmap_rxsync()
274 union e1000_rx_desc_extended *curr = &rxr->rx_base[nic_i]; in em_netmap_rxsync()
HDixgbe_netmap.h390 union ixgbe_adv_rx_desc *curr = &rxr->rx_base[nic_i]; in ixgbe_netmap_rxsync()
430 union ixgbe_adv_rx_desc *curr = &rxr->rx_base[nic_i]; in ixgbe_netmap_rxsync()
/NextBSD/sys/dev/ixl/
HDif_ixl_common.c77 rxr->rx_base = (union i40e_rx_desc *)vaddrs[i*2 + 1]; in ixl_if_queues_alloc()
HDixl_txrx.c584 rxr->rx_base[next_pidx].read.pkt_addr = htole64(paddrs[i]); in ixl_isc_rxd_refill()
610 cur = &rxr->rx_base[i]; in ixl_isc_rxd_available()
704 cur = &rxr->rx_base[ri->iri_cidx]; in ixl_isc_rxd_pkt_get()
HDixl.h408 union i40e_rx_desc *rx_base; member
/NextBSD/sys/dev/ixgbe/
HDixgbe_txrx.c447 rxr->rx_base[next_pidx].read.pkt_addr = htole64(paddrs[i]); in ixgbe_isc_rxd_refill()
473 rxd = &rxr->rx_base[i]; in ixgbe_isc_rxd_available()
513 rxd = &rxr->rx_base[ri->iri_cidx]; in ixgbe_isc_rxd_pkt_get()
HDix_txrx.c1353 rxbuf->addr = rxr->rx_base[i].read.pkt_addr =
1356 rxr->rx_base[i].read.pkt_addr = rxbuf->addr;
1483 bzero((void *)rxr->rx_base, rsize);
1511 rxr->rx_base[j].read.pkt_addr = htole64(paddr);
1534 rxr->rx_base[j].read.pkt_addr = htole64(seg[0].ds_addr);
1785 cur = &rxr->rx_base[i];
2269 rxr->rx_base = (union ixgbe_adv_rx_desc *)rxr->rxdma.dma_vaddr;
2270 bzero((void *)rxr->rx_base, rsize);
HDixgbe.h388 union ixgbe_adv_rx_desc *rx_base; member
HDif_ixgbe.c446 rxr->rx_base = (union ixgbe_adv_rx_desc *)vaddrs[i*2 + 1]; in ixgbe_if_queues_alloc()
994 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error); in ixgbe_get_regs()
995 u32 length = le32toh(rxr->rx_base[j].wb.upper.length); in ixgbe_get_regs()
996 …sbuf_printf(sb, "\tReceive Descriptor Address %d: %08lx Error:%d Length:%d\n", j, rxr->rx_base[j… in ixgbe_get_regs()
/NextBSD/sys/dev/e1000/
HDif_em.h365 union e1000_rx_desc_extended *rx_base; member
HDif_igb.h389 union e1000_adv_rx_desc *rx_base; member
HDif_igb.c3415 rxr->rx_base = (union e1000_adv_rx_desc *)rxr->rxdma.dma_vaddr; in igb_allocate_queues()
3416 bzero((void *)rxr->rx_base, rsize); in igb_allocate_queues()
4155 rxr->rx_base[i].read.hdr_addr = in igb_refresh_mbufs()
4180 rxr->rx_base[i].read.pkt_addr = in igb_refresh_mbufs()
4339 bzero((void *)rxr->rx_base, rsize); in igb_setup_receive_ring()
4365 rxr->rx_base[j].read.pkt_addr = htole64(paddr); in igb_setup_receive_ring()
4391 rxr->rx_base[j].read.hdr_addr = htole64(hseg[0].ds_addr); in igb_setup_receive_ring()
4412 rxr->rx_base[j].read.pkt_addr = htole64(pseg[0].ds_addr); in igb_setup_receive_ring()
4950 cur = &rxr->rx_base[i]; in igb_rxeof()
HDif_em.c3319 rxr->rx_base = (union e1000_rx_desc_extended *)rxr->rxdma.dma_vaddr; in em_allocate_queues()
3320 bzero((void *)rxr->rx_base, rsize); in em_allocate_queues()
4101 em_setup_rxdesc(&rxr->rx_base[i], rxbuf); in em_refresh_mbufs()
4205 bzero((void *)rxr->rx_base, rsize); in em_setup_receive_ring()
4235 em_setup_rxdesc(&rxr->rx_base[j], rxbuf); in em_setup_receive_ring()
4262 em_setup_rxdesc(&rxr->rx_base[j], rxbuf); in em_setup_receive_ring()
4631 cur = &rxr->rx_base[i]; in em_rxeof()